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w29gl256s publication release date: jul 02 , 201 4 revision c 1 256 m - bi t 3.0 - volt parallel flash memory with page mode
w29gl256s publication release date: jul 02 , 201 4 revision c 2 table of contents 1 general description ................................ ................................ ................................ ....................... 8 2 features ................................ ................................ ................................ ................................ ... 8 3 pin configuration ................................ ................................ ................................ ................. 9 4 block di agram ................................ ................................ ................................ ....................... 10 5 pin description ................................ ................................ ................................ ..................... 11 6 introduction ................................ ................................ ................................ ................................ .. 12 7 array architecture ................................ ................................ ................................ ........... 15 7.1 flash main memory array ................................ ................................ ................................ ....... 17 7.2 cfi and device id (cfi - i d) ................................ ................................ ................................ ..... 17 7.3 status register ................................ ................................ ................................ ........................ 18 7.4 data polling status ................................ ................................ ................................ .................. 19 7.5 sector protection control ................................ ................................ ................................ ........ 19 7.5.1 lock register ................................ ................................ ................................ .................. 19 7.5.2 individual protection bits (ipb) ................................ ................................ ....................... 19 7.5.3 ipb lock ................................ ................................ ................................ ......................... 20 7.5.4 dynamic protection bits (dpb) ................................ ................................ ...................... 20 8 functional descriptions ................................ ................................ ................................ ............... 20 8.1 read ................................ ................................ ................................ ................................ ........ 20 8.1.1 random read ................................ ................................ ................................ ................ 20 8.1.2 page read ................................ ................................ ................................ ...................... 21 8.2 device reset operations ................................ ................................ ................................ ......... 21 8.3 standby mode ................................ ................................ ................................ ......................... 22 8.4 automatic sleep ................................ ................................ ................................ ...................... 22 8.5 outp ut disable mode ................................ ................................ ................................ ............... 22 8.6 program methods ................................ ................................ ................................ .................... 23 8.6.1 asynchronous write ................................ ................................ ................................ ....... 23 8.6.2 word programming ................................ ................................ ................................ ........ 23 8.6.3 write buffer programming ................................ ................................ .............................. 25 8.7 program suspend / program resume commands ................................ ................................ . 30 8.8 erase methods ................................ ................................ ................................ ........................ 31 8.8.1 chip erase ................................ ................................ ................................ ...................... 31 8.8.2 sector erase ................................ ................................ ................................ ................... 32 8.9 erase suspend / erase resume ................................ ................................ ............................. 33 8.10 blank check ................................ ................................ ................................ ............................. 34
w29gl256s publication release date: jul 02 , 201 4 revision c 3 8.11 enhanced sector protection methods ................................ ................................ ..................... 35 8.11.1 enhanced sector protection (esp) ................................ ................................ ................ 35 8.11.2 ipb lock ................................ ................................ ................................ ......................... 37 8.11.3 individual protection bits (ipb) ................................ ................................ ....................... 37 8.11.4 dynamic protection bits (dpb) ................................ ................................ ...................... 37 8.11.5 sector protection bit status summary ................................ ................................ ........... 38 8.11.6 lock register ................................ ................................ ................................ .................. 38 8.12 security sector region ................................ ................................ ................................ ............ 39 8.13 monitoring device status ................................ ................................ ................................ ......... 40 8.13.1 status register ................................ ................................ ................................ ............... 40 8.13.2 data polling status ................................ ................................ ................................ ......... 41 8.14 enhanced variable i/o ................................ ................................ ................................ ............ 47 8.15 ready/#busy ................................ ................................ ................................ ........................... 47 8.16 hardwar e data protection options ................................ ................................ .......................... 48 8.16.1 write protect (#wp) ................................ ................................ ................................ ........ 48 8.16.2 write pulse glitch protection ................................ ................................ ....................... 48 8.16.3 power up write inhibit ................................ ................................ ................................ .... 48 8.16.4 logical inhibit ................................ ................................ ................................ .................. 48 8.17 inherent data protection ................................ ................................ ................................ .......... 49 8.17.1 command protection ................................ ................................ ................................ ...... 49 8.18 operating modes and signal states table ................................ ................................ .............. 50 8.19 instruction definition tables ................................ ................................ ................................ .... 51 8.20 common flash interface and device id (cfi - id) ................................ ................................ ... 57 9 electrical specifications ................................ ................................ ................................ ............... 62 9.1 absolute maximum ratings ................................ ................................ ................................ ..... 62 9.1.1 input signal overshoot ................................ ................................ ................................ ... 62 9.2 operating ranges ................................ ................................ ................................ ................... 63 9.2.1 temperature ranges ................................ ................................ ................................ ...... 63 9.2.2 power supply voltages ................................ ................................ ................................ .. 63 9.2.3 power up and power - down ................................ ................................ ........................... 63 9.3 dc characteristics ................................ ................................ ................................ ................... 65 9.4 capacitance characteristics ................................ ................................ ................................ .... 67 10 timing specifications ................................ ................................ ................................ ................... 68 10.1 ac test conditions ................................ ................................ ................................ .................. 68 10.2 power up reset and hardware reset ................................ ................................ .................... 69
w29gl256s publication release date: jul 02 , 201 4 revision c 4 10.2.1 power up reset ................................ ................................ ................................ ............. 69 10.2.2 hardware reset ................................ ................................ ................................ .............. 71 10.3 a c characteristics ................................ ................................ ................................ ................... 72 10.3.1 internal algorithm performance table ................................ ................................ ............ 72 10.3.2 asynchronous read operations ................................ ................................ .................... 73 10.3.3 asynchronous write operations ................................ ................................ ..................... 75 10.3.4 alternate #ce controlled write operations ................................ ................................ ... 81 11 package dimensions ................................ ................................ ................................ ................... 83 11.1 tsop 56 - pin 14x20mm ................................ ................................ ................................ ........... 83 11.2 thin & fine - pitch ball grid array, 56 ball, 7x9mm ( tf bga 56 ) ................................ .............. 84 11.3 low - profile fine - pitch ball grid array, 64 - ball 11x13mm (lfba64) ................................ ....... 85 12 ordering information ................................ ................................ ................................ .................... 86 12.1 ordering part number definitions ................................ ................................ ........................... 86 12.2 valid part numbers and top side marking ................................ ................................ ............. 87 13 history ................................ ................................ ................................ ................................ ......... 88
w29gl256s publication release date: jul 02 , 201 4 revision c 5 table of tables table 5 - 1 pin description ................................ ................................ ................................ ..................... 11 table 6 - 1 w29gl256s address map ................................ ................................ ................................ ... 14 table 7 - 1 w29gl256s sector and memory address map ................................ ................................ .. 17 table 7 - 2 cfi - id address map overview ................................ ................................ ............................ 18 table 8 - 1 write buffer programming command sequence ................................ ................................ . 30 table 8 - 2 sector protection status ................................ ................................ ................................ ....... 38 table 8 - 3 lock register ................................ ................................ ................................ ....................... 38 table 8 - 4 security sector region ................................ ................................ ................................ ......... 39 table 8 - 5 status register ................................ ................................ ................................ ..................... 40 ta ble 8 - 6 data polling status ................................ ................................ ................................ ............... 47 table 8 - 7 interface conditions ................................ ................................ ................................ ............. 50 table 8 - 8 read, write, program and erase definitions ................................ ................................ ....... 51 table 8 - 9 cfi - id (autoselect) definitions ................................ ................................ ............................. 52 table 8 - 10 security sector region command definitions ................................ ................................ ... 52 table 8 - 11 lock register command set definitions ................................ ................................ ........... 53 table 8 - 12 ipb non - volatile sector protection command set definitions ................................ .......... 53 table 8 - 13 global non - volatile sector protec tion freeze command set definitions ......................... 54 table 8 - 14 dpb volatile sector protection command set definitions ................................ ................ 54 table 8 - 15 id (autoselect) address map ................................ ................................ ............................ 57 table 8 - 16 cfi query identification string ................................ ................................ ........................... 59 table 8 - 17 cfi system interface string ................................ ................................ ............................... 59 table 8 - 18 cfi device geometry definition ................................ ................................ ......................... 60 table 8 - 19 cfi primary vendor - specific extended query ................................ ................................ .. 61 table 9 - 1 absolute maximum ratings ................................ ................................ ................................ . 62 table 9 - 2 power up/power - down voltage and timing ................................ ................................ ........ 63 table 9 - 3 dc characteristics ................................ ................................ ................................ ............... 65 table 9 - 4 connector capacitance for fbga (lfbga64) package ................................ ..................... 67 table 9 - 5 connector capacitance for tsop (tsop56) package ................................ ....................... 67 table 9 - 6 connector capacitance for tfbga (tfbga56) package ................................ ................... 67 table 10 - 1 test specification ................................ ................................ ................................ ............... 68 table 10 - 2 power on and reset parameters ................................ ................................ ...................... 69 table 10 - 3 internal algorithm characteristics ................................ ................................ ...................... 72 table 10 - 4 read operation evio = 1.65v to vcc, vcc = 2.7v to 3.6v ................................ ............ 73 table 10 - 5 write operations ................................ ................................ ................................ ................ 75
w29gl256s publication release date: jul 02 , 201 4 revision c 6 table 10 - 6 erase/program operations ................................ ................................ ................................ 78 table 10 - 7 alternate #ce controlled write operations ................................ ................................ ....... 81 table 12 - 1 valid part numbers and markings ................................ ................................ ..................... 87 table 13 - 1 revision history ................................ ................................ ................................ ................. 88 table of figures figure 3 - 1 lfbga64 top view (face down) ................................ ................................ ...................... 9 figure 3 - 2 56 - pin standard tsop (top view) ................................ ................................ ................. 9 figure 3 - 3 tfbga56 top view (face down) ................................ ................................ ...................... 9 figure 4 - 1 simplified block diagram ................................ ................................ ................................ .... 10 figure 8 - 1 word program operation ................................ ................................ ................................ .... 25 figure 8 - 2 write buffer programming operation with data polling status ................................ .......... 28 figure 8 - 3 write buffer programming operation with status register ................................ ................ 29 figure 8 - 4 sector erase operation ................................ ................................ ................................ ....... 33 figure 8 - 5 enhanced sector protection ipb program algorithm ................................ ......................... 36 figure 8 - 6 data# polling algorithm ................................ ................................ ................................ ....... 42 figure 8 - 7 toggle bit program ................................ ................................ ................................ ............. 46 figure 9 - 1 max negative overshoot waveform ................................ ................................ ................... 62 figure 9 - 2 positive overshoot waveform ................................ ................................ ............................ 62 figure 9 - 3 power - up ................................ ................................ ................................ ............................. 64 figure 9 - 4 power - down and voltage drop ................................ ................................ ........................... 64 figure 10 - 1 device under test setup ................................ ................................ ................................ .. 68 figure 10 - 2 input switching test waveforms ................................ ................................ ...................... 68 figure 10 - 3 power up reset ................................ ................................ ................................ ................ 70 figure 10 - 4 hardware reset ................................ ................................ ................................ ................ 71 figure 10 - 5 back to back read (tacc) operation ................................ ................................ ............... 73 figure 10 - 6 back to back read operation (trc) ................................ ................................ ................. 74 figure 10 - 7 page read ................................ ................................ ................................ ........................ 74 figure 10 - 8 back to back wri te operation ................................ ................................ ........................... 75 figure 10 - 9 back to back (#ce vil) write operation ................................ ................................ .......... 76 figure 10 - 10 write to read (tacc) operation ................................ ................................ ..................... 76 figure 10 - 11 write to read (tce) operation ................................ ................................ ........................ 77 figure 10 - 12 read to write (#ce vil) operation ................................ ................................ ................ 77 figure 10 - 13 read to write (#ce toggle) operation ................................ ................................ ........... 78
w29gl256s publication release date: jul 02 , 201 4 revision c 7 figure 10 - 14 program operation ................................ ................................ ................................ .......... 79 figure 10 - 15 chip/sector erase operation ................................ ................................ .......................... 79 figure 10 - 16 data# polling (during internal algorithms) ................................ ................................ ..... 80 figure 10 - 17 toggle bit (during internal algorithms) ................................ ................................ ........... 80 figure 10 - 18 dq2 vs. dq6 comparison timing ................................ ................................ .................. 81 figure 10 - 19 back to back (#ce) write operation ................................ ................................ .............. 82 figure 10 - 20 (#ce) write to read operation ................................ ................................ ....................... 82 figure 11 - 1 tsop 56 - pin 14x20mm package ................................ ................................ ..................... 83 figure 11 - 2 tfbga - 56, 7x9mm package ................................ ................................ ............................ 84 figure 11 - 3 lfbga 64 - ball 11x13mm package ................................ ................................ ................... 85 figure 12 - 1 ordering part numbering ................................ ................................ ................................ .. 86
w29gl256s publication release date: jul 02 , 201 4 revision c 8 1 general description the w29gl256s parallel flash memory provides a storage solution for embedded system applications that require better performance, lower power consumption and higher density. this product fabricated on 58 nm process technology. this device offer s a fast page access time as fast as 15ns with a corresponding random access time as fast as 90ns. it features a write bu ffer that allows a maximum of 256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming time than standard programming algorithms. the w29gl256s also offers special features such as compatible manufacturer id that m akes the device industry standard compatible without the need to change firmware. 2 features ? 58 nm technology ? x16 data bus ? 256 - word (512 - byte) programming buffer o programming in page multiples, up to a maximum of 512 bytes ? asynchronous 32 - byte page read ? single word and multiple program on same word options ? sector erase o uniform 128 - kbyte sectors ? enhanced sector protection (esp) ? volatile and non - volatile protection methods for each sector ? security sector region ? 1024 - byte one time program (otp) array divided into two 512 - byte lockable regions ? suspend and resume commands for program and erase operations ? status register, data polling, and ready/b usy pin methods to determine device status ? cfi (common flash interface) support ? single supply ( vcc ) for read / program / erase (2.7v to 3.6v) ? enhanced variable i/o feature o enhanced i/o voltage range (e vio ): 1.65v to vcc ? wide temperature range ( - 40c to +85c) ? more than 100,000 erase /program cycles ? 20 - year data retention typical ? packaging options o 56 - pin tsop , 14x20mm o 56 - ball tfbga, 7x9mm o 64 - ball lf bga, 13x 11 mm
w29gl256s publication release date: jul 0 2 , 201 4 revision c 9 3 pin configuration figure 3 - 1 lfbga64 top view (face down) figure 3 - 2 56 - pin standard tsop (top v iew ) figure 3 - 3 tfbga56 top view (face down) a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 3 n c a 7 r y / # b y # w e a 9 a 1 3 n c b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 a 4 n c a 1 7 # w p # r e s e t a 8 a 1 2 a 2 2 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 a 2 n c a 6 a 1 8 a 2 1 a 1 0 a 1 4 a 2 3 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 a 1 n c a 5 a 2 0 a 1 9 a 1 1 a 1 5 e v i o e 1 e 2 e 3 e 4 e 5 e 6 e 7 e 8 a 0 d n u d q 0 d q 2 d q 5 d q 7 a 1 6 v s s f 1 f 2 f 3 f 4 f 5 f 6 f 7 f 8 # c e e v i o d q 8 d q 1 0 d q 1 2 d q 1 4 r f u n c g 1 g 2 g 3 g 4 g 5 g 6 g 7 g 8 # o e r f u d q 9 d q 1 1 v c c d q 1 3 d q 1 5 n c h 1 h 2 h 3 h 4 h 5 h 6 h 7 h 8 v s s n c d q 1 d q 3 d q 4 d q 6 v s s n c nc nc a 16 rfu vss dq 15 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 vcc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 # oe vss # ce a 0 rfu evio a 23 a 22 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 19 a 20 # we # reset a 21 # wp ry / # by a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 rfu dnu 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 b 8 c 8 d 8 e 8 f 8 g 8 b 1 c 1 d 1 e 1 f 1 g 1 a 2 b 2 c 2 d 2 e 2 f 2 g 2 h 2 a 3 b 3 c 3 d 3 e 3 f 3 g 3 h 3 a 4 b 4 c 4 f 4 g 4 h 4 a 5 b 5 c 5 f 5 g 5 h 5 a 6 b 6 c 6 d 6 e 6 f 6 g 6 h 6 a 7 b 7 c 7 d 7 e 7 f 7 g 7 h 7 a 3 a 2 a 1 a 0 # c e d n u a 6 a 5 a 4 v s s # o e d q 0 a 7 d q 8 n c a 1 8 a 1 7 d q 1 d q 9 d q 1 0 n c d q 2 # r e s e t r y / # b y d q 3 v c c # w p d q 1 1 a 2 3 a 2 0 d q 4 e v i o # w e r f u a 1 9 a 9 a 1 0 d q 6 d q 1 3 d q 1 2 a 8 d q 5 a 1 2 a 1 3 a 1 4 r f u d q 1 5 d q 7 a 1 1 d q 1 4 a 1 5 a 2 1 a 2 2 a 1 6 r f u v s s
w29gl256s publication release date: jul 0 2 , 201 4 revision c 10 4 block diagram figure 4 - 1 simplified block diagram control decoder main array output buffer #ce #oe #we ry/#by #reset # wp a0 a23 . . . . . . . . . . . . . . . . . . . . . dq15 dq0 . . . . . . . . . . . . . . vcc evio vss
w29gl256s publication release date: jul 0 2 , 201 4 revision c 11 5 pin description table 5 - 1 pin description symbol signal type pin name a0 - a23 input address inputs dq0 - dq15 i/o data inputs/outputs #ce input chip enable, device selected at v il #oe input output enable, output at v il and high - z at v ih #we input write enable, write mode at v il and read mode at v ih #wp input hardware write protect, highest & lowest sector protect at v il #reset input hardware reset, device logic to standby and ready to read. ry/#by output ready/busy status , indicates whether an embedded algorithm is in progress or complete. at v il , the device is actively engaged in an embedded algorithm such as erasing or programming. at high - z, the device is ready for read or a new command write - requires external pull - up resistor t o detect the high - z state. multiple devices may have their ry/#by outputs tied together to detect when all devices are ready. vcc power supply power supply e vio power supply enhanced variable io supply vss power supply ground nc - no connection
w29gl256s publication release date: jul 0 2 , 201 4 revision c 12 6 introduction the w29gl256s is a 3v, 256 - mbit, non - volatile, flash memory device with variable i/o . the device has a bus width of 16 - bits (2 - bytes/1 - word) and word address boundaries are what are used. all read accesses provide 16 bits of data on every bus cycle. every write cycle transfers 16 bits of data on the bus. xip and data storage flash memories are combined features of the w29gl256s. this enables the abi lity of fast programming speeds and reduced random access time of xip flash in higher densities. read access to any random location takes 90 ns to 100 ns depending on device i/o power supply voltage. each random access reads an aligned group of data of 32 - bytes called a page. other words within the same page may be read by changing only the low order 4 bits of word address. while in the same page, access could take between 15 ns to 30 ns. this read operation is referred as page mode. higher word address bits will select a different page and begin another initial access. all read accesses are asynchrono us. the device control logic is divided into two parallel operating subsections, the command state machine (csm) and the write state controller. device level signals with the host system during read and write transfers are monitored by the csm as needed for th e inputs and drive outputs. csm delivers data from the current entered address map on read operations; places write address and data information into the write state controller command memory; signals the write state controller of power level changes, writ e operations and hardware reset, the write state controller looks in the command memory, after a write operation, for correct command sequences and performs internal algorithms that are related. within the w29gl256s lie internal complex sequential operatio ns or algorithms that are necessary to change the state of non - volatile data in the memory array. the internal write state controller manages all device algorithms. the main array data, programming and erasure are the main algorithms that are performed. wh en the host system sends command instructions to the flash device address space and write state controller receives these commands, provides status information during the progress of internal algorithms and performs all the necessary steps to complete the command. a logical 1 bit is considered an erased cell. changing a bit from a logical 1 to a logical 0 is considering programming. note, only an erase operation is able to change a 0 to a 1. a restriction to an erase operation is a minimum of an entire sect or (sector erase), which is a 128 - kbyte aligned and length group of data is erased or the entire array can be erased (chip erase). winbond ships the w29gl256s with all sectors erased.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 13 the w29gl256s programming algorithm transfers volatile data from a write buffer to a non - volatile memory array line; this is called write buffer programming. the size of the buffer is 256 - words (512 - bytes). 1 to 256 words can be written at any location in the write buffer prior to executing the programming operation. the progr amming operation can only be performed on an aligned group of 512 bytes in the flash array which is referred to as a line. after the completion of any write buffer operation or a reset, the buffer is refreshed to all 1s. by default any location that has n ot be written to a 0 are filled with 1s. each page of data that was loaded into the write buffer during a programming operation, the memory array data is unaffected by 1s in the write buffer as it is transferred to a memory array line. program and erase operations may be affected by the enhanced sector protection (esp) methods, preventing any erasure or programming in a sector that may have been previously protected.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 14 table 6 - 1 w29gl256s address map addresses value description a3 - a0 16 word selection a7 - a0 256 write buffer internal address a15 - a4 4096 page selection a15 - a8 256 write - buffer - line selection a23 - a16 256 sector selection
w29gl256s publication release date: jul 0 2 , 201 4 revision c 15 7 array architecture there are several separate address spaces (i.e., memory map overlay) that may appear within the address range of the flash memory device. only one mmo can exist or be entered at a time. ? main memory array ? this non - volatile area is u sed for storage of data that may be randomly acces sed by asynchronous read operations . ? id/cfi ? a winbond factory programmed area for device characteristics information. it contains the common flash interface (cfi) and device identification (id) information tables. ? security sector region (ssr) ? a non - volatil e / one time programmable (otp) memory array used for winbond factory and customer programmable permanent data . ? lock register ? this otp non - volatile word is used to configure the enhanced sector protection ( esp ) features and lock the ssr. ? individual protec tion bits (ipb): ? a non - volatile flash memory array with one bit for its associated s ector. p rogram ming this bit protects th at s ector from programming and erasure . ? ipb lock ? program and erase protection for the ipb bits . when the v olatile register bit is enable d no programming or erasing of the ipb bits is prohibited . ? dynamic protection bits (dpb) ? similar to the ipb scheme, this v olatile array with one bit for each s ector can protect its associated s ector from erasure and programming while the device is p owered . ? status register ? internal a lgorithm status monitoring can be done using this v olatile register. ? data polling status: ? l egacy software compatible v olatile register used as an alternat ive to the status register to monitor internal algorithm status. the main memory array is the primar y and default address space. this area at any time may be overlaid by one othe r address space . all the aforementioned address space s are considered as a memory map overlay (mmo). each mmo replaces the entire address range of the main array. addresses outside the current mmo address map are considered as not defined and are reserved for
w29gl256s publication release date: jul 0 2 , 201 4 revision c 16 future use. read access is possible outside of an mmo address map and will return non - valid (undefined) data. what appears in the flash devic e address space at any given time is one of four address map modes : ? read mode ? memory map overlay (mmo) mode ? status register (sr) mode ? data polling mode in read m ode the entire flash memory array may be directly read. read mode is entered during power up , after a hardware reset, command reset completion , or when an internal algorithm is suspended , all of which is controlled by the write state controller . while in the read mode , command accesse s are permitted when an internal algorithm is suspended . there ar e subsets of commands that will be accepted in read m ode while an internal algorithm is suspended . the status register read command can be issued in any mode. t his execution will cause the mmo of the status register to appear in the device address space at every word address location . to do this, the device interface waits for a read access, ignoring any write access . the content of the status register is presented at the next read access , a fter which it exits the status register mmo, and r eturns to the pre vious mode in which the status register read command was received. while the write state controller is performing an internal a lgorithm, such as a non - volatile memory array program or an erase operation , none of the m ain memory array is accessible because , the entire flash device address space is replaced by the mmo of the data polling status at every word location in the device address space. while in an internal algorithm operation , only the status register read command or a program / erase suspend command will be accepted, ignoring all other commands. he n ce, no other mmo may be entered. the data polling mmo is visible during an internal algorithm operation and once a suspend command has been executed it is present up to the moment t he device sus pends the internal algorithm. when the internal a lgorithm is suspended the data polling mmo is exited and the main memory array data is available again . t he data polling mmo is activated again when the suspended internal a lgorithm operation is resumed . at the completion of an internal algorithm operation , the data polling mmo is exited and the device goes back to operation from which it was called.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 17 as mentioned previously, o nly one mmo may exist at any one time. device commands affect only the curr ently entered mmo. not all commands are valid for each mmo. for a listed of valid commands, see the command definition t ables in mmo section s of the table. some mmos have non - volatile data that can be programmed ? individual protection bits (ipb), also e rase capable ? lock register ? security sector region operating in a non - volatile mmo mode while performing a program or erase command , the mmo is not readable while the internal a lgorithms is active. as soon as the function has completed, the mmo mode remains active and is again readable. suspend and resume commands are ignored for these non - volatile modes while these internal algorithms are active . 7.1 flash main memory array the w29gl256s family is comprised of uniform 128kb sector size architec ture . the t able below shows the sector architecture of the w29gl256s device. table 7 - 1 w29gl256s sector and memory address map sector sector address a23 - a16 sector size (kbyte) x16 start / finish sa00 0000000 128 0000 000h 000ffffh sa01 0000001 128 0010000h 001ffffh . . . . . . . . . . . . . . . sa254 11111110 128 0fe0000h 0feffffh sa255 11111111 128 0ff0000h 0ffffffh note: this table has been reduced to show relative sector information for the entire devices individual s ectors and their address ranges ( sectors sa02 - sa253 are not shown ) . 7.2 cfi and device id ( cfi - id ) there are two methods for systems t o identify the type of flash memory i nstalled in the system. the first method is called the common flash interfac e (cfi). the second method called autoselect, which is now referred to as device identification (id). device identification (id), a command i s used to enable a memory map o verlay where up to 16 word locations can be read to get jedec manufacturer identifi cation (id), device id, and some configuration and protection status information from the flash memory.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 18 the common flash interface ( cfi ) command enable s a memory map o verlay where a table of standard information about how th e flash memory is organized and operates can be read . typically, these two address spaces have used separate commands and had separate overlays and are non - overlapping, so they actually can be combined in a single overlay. either of these two commands can be used to access the combined autoselect (id) and cfi overlay . the cfi - id address map o verlays the flash array data of the sector selected by the address used in the cfi - id enter command. while the cfi - id mmo is entered , the content of all other sectors is undefined. address map start s at location 0 of the selected sector. data is considered as undefined past the maximum defined address of the cfi - id mmo to the maximum addr ess of the selected sector . to enter the manufacturer id (autoselect) and common flash interface (cfi) mmo command modes see the instruction definition table . table 7 - 2 cfi - id address map overview word address description read / write (sa) + 0000h to 000fh device id (traditional autoselect values) read only (sa) + 0010h to 0079h cfi data structure read only (sa) + 0080h to ffffh undefined read only for the complete address map see the device id and common interface table s. 7.3 status register the status r egister , memory map overlay ( mmo ) contains status for internal algorithms in a single volatile word format . when the read command for the status register is issued, status at the time of captured is presented in the register and the mm o is entered. all word locations in the device address space contain t he status register information . status register exits the mmo mode after the first read access and returns to the address space map in use when the status register read command was issue d.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 19 7.4 data polling status the data polling status , memory map overlay ( mmo ) monitors the progress of internal algorithms which is contained in a single volatile word. following the last write cycle of any command sequence that initiates an internal algorithms, the data polling status will be entered . internal algorithms are initiated by one of the following commands : ? blank check ? chip erase ? sector erase ? er ase resume / program resume ? word program ? program buffer to flash ? program resume enhanced method ? lock register program ? ipb program ? all ipb erase at all word locations in the device address space, t he data polling status word appears. data polling status mmo is exited and the device address space returns to the address map mode where the internal algorithms was started at the completion of the internal algorithms. 7.5 sector protection control 7.5.1 lock register the lock r egister , memory map overlay ( mmo ) mode contain s a single word of one time programmable ( otp ) memory. when the mmo mode is entered the lock register appears at all word locations in the device address space. winbond recommends for future compatibility to read or program the lock register only at locati on 0 of the device address space. 7.5.2 individual protection bits (ipb ) the ipb , memory m ap o verlay (mmo) mode contains a non - volatile bit in each s ector in the device. when the mode is entered, the ipb bit for a chosen sector appears in the least significant bit (lsb) of each word in that sector. the non - volatile protection status for that sector is displayed by r eading any word location, where the lsb indicates whether or not the sector is protected . the sector is prote cted against programming and erase operations if the bit is has been programmed to a 0. the sector is not protected by the ipb if the bit has been erased to a 1. note ; there are other features of
w29gl256s publication release date: jul 0 2 , 201 4 revision c 20 the enhanced sector protection (esp) that can protect sector s. winbond recommends for future compatibility, to read or program the ipb only at word location 0 of the sector. 7.5.3 ipb lock the ipb lock , memory map overlay (mmo) contains a single volatile bit of memory. programming or erasing of the ipb is controlled by i pb lock . ipb is protected against programming and erase operations , if the bit is 0. the ipb is not protected, i f the bit is 1. when the ipb lock mode is entered , the ipb lock bit appears in the least significant bit (lsb) of each word in the devi ce addres s space. winbond recommends for future compatibility, to read or program the ipb lock only at word location 0 of the device. 7.5.4 dynamic protection bits (dpb) the dpb memory map overlay (mmo) contains one volatile bit of memory for each sector . the dpb bit for a sector appears in the least significant bit (lsb) of each word in the sector after entering the dp b mode . reading any word in a sector displays the protection status for that sector. sectors are protected during program and erase operations, i f the dpb is 0 and unprotected i f the bit is 1. note there are other features of esp that can protect the sector . winbond recommends for future compatibility to read, set, or clear the dpb only at word location 0 of the sector. 8 functional descripti ons 8.1 read 8.1.1 random read t he memory device is select ed by driving chip enable (#ce) low and the device will leave the standby mode . if write enable ( #we ) is disabled, driven high w hile #ce is low , a random read operation is started. the particular data output will depends on the mmo mode and the specific address provided . the data output is presented on dq15 - dq0 when #ce is low , output enable ( #oe ) is low , #we is high , address is stable, and the asynchronous access times are met . the address access time (t acc ) is de fined to be equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is defined as the delay from a stable #ce to valid data on the outputs. the #oe signal must be low for at least the period of the output enable tim e (t oe ), before valid read data is available at the outputs .
w29gl256s publication release date: jul 0 2 , 201 4 revision c 21 device outputs will provide valid read data from the currently active address map mode at the end of the random read access time from address stable (t acc ), #oe active (t oe ), or #ce active (t ce ), whichever happens last. a list of other transitional states during random read operation; ? a new random read access begins i f #ce remains low and any address [ 23:4] signals change to a new value. ? in order to get back to back accesses, requires an address c hange to initiate the second access and #ce to remains low between accesses read mode with outputs disable, if #ce remains low and #oe goes . ? write mode, if #ce remains low , #oe goes high , and #we goes low . ? standby mode, if #ce returns high . 8.1.2 page read as in the random read mode , a random read access sequence is required. t hen if #ce remains low , #oe remains low , address[ 23 : 4 ] signals remain s unchanged , and any of the address[3:0] signals have change, then a new access within the same page (32 - byte) begins with data appearing on dq15 - dq0 . the page read is much faster (t pacc ) than a random read access. if #ce goes high and returns low for another access, a random read access is performed and time is required (t acc or t ce ). 8.2 device reset operations the hardware reset (#reset) input pin provides a hardware method of resetting the device to a standby mode . immediately after issuing a hardware reset, driving #reset low for at least a period of t rp : ? any operations in progress are terminated, ? memory map overlays (mmo ) is exited. ? all outputs are set to high - z. ? the status register is reset. ? the write state controller goes to the standby mode. ? #ce is ignored for a period of (t rph), during the reset operation. ? #ce must be held h igh to meet the reset current specification (i cc5 ). note: an operation that was interrupted should be reinitiated to ensure data integrity. an operation command sequence should be executed once the device is ready.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 22 8.3 standby mode standby is the default, minimum power condition while the device is not selected (#ce = high ). all inputs are ignored in this mode and all outputs , except ry/#by are at high - z . the write state controller direct output of the ry/#by determines its state and is not controlled by other devices or interfac es . 8.4 automatic sleep when addresses remain stable for t acc + 30 ns, the device will automatically enter the auto sleep mode and latches the output data. data on the output pins depends on the level of the #oe signal. the automatic sleep mode is designed to reduce device interface current (i cc6 ). #oe signal levels are independent of the automatic sleep mode current. the a utomatic sleep mode current (i cc6 ) specifications can be found in the dc characteristics table s . its important to note that slow clock dura tions help reduce current consumption when the automatic sleep mode goes active. during slow clock periods, read and write cycles may extend many times their length versus when the clock is operating at high speed. even when the chip enable is low throughout these extended data transfer cycles, the memory device command state machine (csm) will enter the automatic sleep mode . this keeps the device in the automatic sleep power level for most of the extended duration of the data transfer cycles. obvi ously this method is beneficial rather than consuming full read power all the time that the device is selected . note , the write state controller operates independent of the automatic sleep mode of the command state machine (csm) and will continue to draw c urrent during an active internal algorithm. only when both entities are in their standby modes is the standby level current minimized . 8.5 output disable mode when the #ce signal is driven low , either a controlled read or write data transfer may begin . when th ere is a period at the start of a data transfer when chip enable is low , address has become valid, #we is high and output enable (#oe) is high . during this point a random read process is started while the data outputs remain at high - z (output disabled) . dr iving the #oe signal low , the device interface transitions to the random read mode and output data is actively driven. if in the event the write enable ( #we ) signal is driven low , the device interface transitions to the write mode. the host system interfac e should never drive #oe and #we low at the same time; this will prevent conflicts with the device.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 23 8.6 program methods 8.6.1 asynchronous write when #we goes low after ce is low , there is a transition from one of the read modes to the write m ode . if #we is low before #ce goes low , there is a transition from the standby mode directly to the write mode without beginning a read access. at this point setting output enable (#oe) high will start a write data transfer. address is captured by the falling edge of #we o r #ce, whichever occurs last . data is captured by the rising edge of #we or #ce, whichever occurs first. a #we controlled write access is w hen the #ce goes low before #we goes low and stays low after #we goes high . when #we are high and #ce goes high , ther e is a transition to the standby mode . if #ce remains low and #we goes high , there is a transition to the read with output disable state. a #ce controlled write mode is when #we is low before #ce goes low , the write transfer is started by #ce going low . t hen if #we goes low after #ce goes h igh , the address and data is latch by the rising edge of #ce. another #ce controlled w rite mode access is w hen #we is low before #ce goes low and remains low after #ce goes high . this is a #ce controlled write transitions to the standby mode . an address change is required to initiate a read access following a write access, if #ce remains low between accesses. an address change is required to initiate the second write access in a back to ba ck write in which #ce remains low between accesses. the write state controller command memory array is not readable by the host system and has no mmo. its purpose is to examine the address and data in each write transfer to determine if the write is a lega l command sequence. if the command sequence is correct, the write state controller will initiate the appropriate internal algorithms. 8.6.2 word programming word programming program s a single word anywhere in the m ain memory array. the wor d programming command i s a four write cycle sequence. this is done by writing the unlock write c ommand in the first two cycles, a program set up command in the third cycle and f inally, in the
w29gl256s publication release date: jul 0 2 , 201 4 revision c 24 fourth cycle the program a ddress and data are written. this will initiate the internal word program algorithm. no further input controls are required. the internal algorithm generates all the program ming pulses and programmed cell verifications . when the internal word program algorithm is complete, the write state controller then returns to its standby mode. program operation status can be determined by monitoring the ry/#by output, reading the status register, or by using data polling status . program suspend is the only command that can be written to the device during the internal program a lgorithm , all others are ignored. h owever , a hardware reset (#reset = v il ) will immediately terminates the programming operation . then after t rph time, returns the device to read mode. it is recommended to reinitiate the word program command sequence after the device has completed the hardware reset operation to insure data integrity. the security sector region (ssr) mode may also use t he word programming command when is entered. the word programming command has a modified version without unlock write cycle s when it is used for programming the lock register and ipb mmos. the same command is also used to change volatile bits when entered in to the ipb lock, and dpb mmos. see the instruction definition t able s for program command sequences.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 25 figure 8 - 1 word program operation 8.6.3 write buffer programming a 512 - byte address range write buffer is used to program data within an aligned 512 - byte boundary line, (example, addresses: 100h to 1ffh). hence, a writ e buffer programming operation must be setup on a line boundary. if the program ming operation is less than 512 - bytes , it may start on any word boundary , but may not cross a write - buffer - line boundary. all bit locations in the buffer at the start of a write buffer programming operation are in the ones state (ffffh/word). thus, any locations not loaded will retain the existing data. the main memory array and the secure sector region (ssr) are the areas that are supported by the write buffer programming oper ation. it is possible to program from 1 bit , up to 512 bytes in one write buffer programming operation. the recommended write buffer method is to only write each page once in a multi - page scenario. programming should be done in full lines of 512 bytes setu p on 512 - byte boundaries, for the very best performance . to initiate a write buffer progr amming operation, the first 2 cycles are the unlock write commands . the 3 rd write cycle contains the write to buffer command with the program targeted sector address (sa). the fou rth cycle is to write the number of planned word locations minus 1. this will indicate the
w29gl256s publication release date: jul 0 2 , 201 4 revision c 26 number of write buffer addresses that are to be loaded with data . this also indicates when to expect the program buffer to flash confirm command. the wr ite to buffer command and the write word count command sector address es must match . in order to program , the sector must be unlocked (unprotected). cyc le 5 , the starting address / data combination is writ t e n . this will be the first address / data pair to b e programmed, and selects the write - buffer - line address. the operation will abort and return to the initiating state if t he sect or a ddress does not match the w rite to buffer sector address . in the following cycles, each address / data pai rs must be in sequential order and a ll write buffer address es must be within the same line, otherwise the operation will abort and return to the initiating state. for each data write operation, th e wc counter will decrement and every write is data being loaded into the write buffer. during the write buffer loading period no commands are accepted . the only way to stop writing data to the write buffer is to abort the write to buffer command. this is done by writing an invalid address that is outside the write buffer line o f the programming operation. the program buffer to flash command must be issued immediately after the specified number of write buffer locations has been loaded at the sector address. at this point the program algorithm starts and the device status will b e busy. the internal program a lgorithm will program and verifies the d ata that has been programmed into the selected sector of the main memory array . no control signals or timing parameters during this internal operation is required . the operation will abo rt and return to the initiating state anytime an incorrect number of write buffer locations have been loaded. the abort occurs because anything other than the expect program buffe r to flash command happened at the end of the word count. the write - buffer in ternal programming operation can be suspended using the program suspend command. when the internal program a lgorithm is complete, the write state controller then returns to the write state controller standby mode where the programming operation was started . under the following conditions the write buffer programming sequence will be aborted: ? the word count cannot exceed a value greater than the buffer size, which is 255 (256 minus 1). ? the write to buffer command cannot contain an address that is outside the line. ? after the write word count number of data words is loaded the program buffer to flash command is not issued data polling status, reading the status register, or monitoring the ry/#by output can determine the status of the program operation. an abor t of the write buffer command will occur immediately after an invalid condition, and will indicate a program fail in the status register at program status bit (b it
w29gl256s publication release date: jul 0 2 , 201 4 revision c 27 4 =1), because of the write buffer abort status bit (bit 3) equals 1 . a clear status register command may be issued to clear the program status bit or the next successful program operation wi ll clear the failure status bit . caution should be taken when stopping t he write buffer prog ramming sequence by the following methods : power cycling the device or a hardware reset . using either of these methods may leave the area being programmed in an unknown state with unstable or invalid data. if this is the ca se reprogrammed with the same data or performing an erased to ensure data values are properly programmed or erased.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 28 figure 8 - 2 write buffer programming operation with data polling status notes: 1. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. 2. if this flowchart location was reached because dq5 = 1, then the device failed. if this flowchart location was reached because dq1 = 1, then the write buffer operation was aborted. in either case the proper reset command must be written to the device to return the device to read mode. write - buffer - programming - abort - rest if dq1 = 1, either software reset or write - buffer - programming - abort - reset if dq5 = 1. 3. see instruction definitions tables for the command sequence as required for write buffer programming. 4. when secto r address is specified, any address in the selected sector is acceptable. however, when loading write - buffer address locations with data, all addresses must fall within the selected write - buffer page. w r i t e t o b u f f e r c m d ( s a ) w o r d c o u n t m i n u s - 1 , ( s a ) w r i t e b e g i n n i n g a d d / d a t a w c = 0 ? a b o r t w r i t e t o b u f f e r w r i t e t o a d i f f e r e n t ( s a ) w r i t e n e x t a d d / d a t a 4 w r i t e p r o g r a m t o f l a s h c o n f i r m ( s a ) r e a d d q [ 7 : 0 ] / w a d d = l a s t l o a d e d a d d d q 7 = d a t a ? d q 5 = 1 ? d q 7 = d a t a ? d q 1 = 1 ? r e a d d q [ 7 : 0 ] / w a d d = l a s t l o a d e d a d d f a i l / a b o r t 2 p a s s w c = w c - 1 w r i t e t o b u f f e r a b o r t e d . m u s t w r i t e t o b u f f e r a b o r t r e s e t t o r e t u r n t o r e a d m o d e n o y e s y e s y e s n o n o n o y e s n o n o y e s y e s
w29gl256s publication release date: jul 0 2 , 201 4 revision c 29 figure 8 - 3 write buffer programming operation with status register notes: 1. see instruction definitions tables for the command sequence as required for write buffer programming. 2. when sector address is specified, any address in the selected sector is acceptable. however, when loading write - buffer address locations with data, all addresses must fall within the selected write - buffer page.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 30 table 8 - 1 write buffer programming command sequence address data sequence comment 555 aa unlock command 1 . 2aa 55 unlock command 2 . sa 0025h write to buffer command at sector address . sa wc number of locations at sector address . wc = number of words to program minus 1 wc set to 1 = 2 words to program. example starting address pd write starting address / data pair . selects write - buffer - page and loads first address/data pair. wbl pd write next address / data pair . all addresses must be within the selected write - buffer - page boundaries, and have to be loaded in sequential order. wbl pd write last address/data pair . all addresses must be within the selected write - buffer - page boundaries, and have to be loaded in sequential order. sa 0029h write buffer program confirm at sector address . this command must follow the last write buffer location loaded, or the operation will abort. device goes busy. legend: sa = sector address (non - sector address bits are don't care. any address within the sector is sufficient.) wbl = write buffer location (must be within the boundaries of the write - buffer - line specified by the starting address.) wc =word count pd = program data 8.7 program suspend / program resume commands an internal programming operation can be interrupted so that data can read from any non - suspended boundary line by using the program s uspend command . during a programming process and the program suspend command is written, the programming operation will halt within the period of t psl and the status bits will be updated . when writing the program suspend command addresses are don' t care. program suspend has two commands available; the erase/ program suspend command (b0h command code) , which is a combined legacy command. t he program suspend command (51h
w29gl256s publication release date: jul 0 2 , 201 4 revision c 31 command code). program resume also has two possible commands ; the erase / program resume command (30h command code) legacy combined command. program resume command (50h command code). it is recommended not to use the combine erase/program suspend or the combined erase/program resume commands for programming and for the erase suspend an d resume use the legacy combined commands . after suspending the program ming operation , any non - suspended line of array data can be read . if during an erase suspended operation to start a programming operation that was suspended, only addresses not in the e rase or program suspend may be read. the device returns back to program operation and the status bits are updated a fter the p rogram resume command is executed . monitoring the status register or using the data polling method, the programming operation statu s can be determined. during program suspend, valid a cces ses and commands : ? any non - erase suspended sector can be read ? any non - program suspended line can be read . ? status read command ? exit mmo or command set exit ? program resume command program resume command must be executed to exit the program suspend mode to continue the programming operation. resume command s are ignored once the device has returned to the programming operation. after the device has resumed programming operation a program suspend command ca n be re - written. programming operations can be interrupted as often as necessary but, the minimum requirement between a program resume and the next program suspend must be greater than or equal to t prs . not supported is program susp end and resume mode whi le entered in an mmo. likewise, there is no support w hile in program suspend to enter into mmo . 8.8 erase methods 8.8.1 chip erase the entire main memory array is erased by chip erase function . the internal erase a lgorithm will first program and verifies the entire m emory prior to an electrical erase. all locations within the device will contain ffffh a fter a successful chip erase . there is no need to provide any control signals or timing parameters during this operation . initiating the chip erase command sequence re quires writing two
w29gl256s publication release date: jul 0 2 , 201 4 revision c 32 unlock cycles, the a setup command cycle, t wo additional unlock write cycles and then the chip erase command, which in turn actives the internal erase a lgorithm. while the internal erase operation is in progress, no data can be read from the device. chip erase operation status can be determined by reading the status register or using data polling. o nly a status read, hardware reset or power cycle are valid , once the chip erase opera tion has begun, ignoring a ll other commands. when the internal erase algorithm has finished, the write state controller will return to the standby mode. however, in the case of a hardware reset or power cycle , the erase operation immediately terminates and returns to read mode after a period of t rph . in the event the chip erase operation is terminated and to insure the integrity of the device data , the chip erase command sequence should be reinitiated once the device has returned to an idle state. if a sect or is protected during chip erase, the internal erase algorithm will ignore the protected sector and move on to the next sector erase. 8.8.2 sector erase the s ector erase function erases a selected 128 - kbyte sector in the main memory array. the internal erase a lgorithm programs and verifies the select sector prior to an electrical erase. there are no requirements for any control signals or timing parameters during this internal operation. all locations within the erased sector will contain an ffffh pattern, indi cating a successful sector erase. if the sector has been protected, the sector will not be erased. reading the status register or using data polling can be used to determine the status of the erase operation . it takes six cycles to perform a sector erase c ommand sequence; w riting two u nlock cycles, followed by a set up command , writing t wo more unlock cycles , and the sector erase command that contains the address of the desired sector to be erased. the status register read and erase suspend commands are the only valid commands that can be used after the s ector erase operation has commenced, ignoring all other commands . the sector erase operation and be terminated abruptly by a hardware reset at which time the device returns to read mode after a period t rph . if this is the case , the sector erase command procedure must be redone again once the device has completed the reset operation to ensure integrity of the data.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 33 figure 8 - 4 sector erase operation 8.9 erase suspe nd / erase resume the erase suspend command interrupt s a sector erase operation making it possible to read data or program data in the main memory array. the erase suspend command is valid when a sector erase or a program operation is in progress . executin g an erase suspend command during a chip erase operation will be ignored . the device requires a maximum of t esl to suspend the erase operation and update the status bits any time the erase suspend command is executed dur ing the a sector erase operation. o nce in the erase - suspend mode, the main memory array can be read or programmed. reading at any address outside erase - suspended sectors produces valid data. reading within the suspended sectors will result in invalid data. monitoring the status register or data polling can be used to determine t he status of the device actively performing an eras e or erase - suspended function.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 34 the write state controller will return the device back to the erase - suspend mode after a program operation has completed that was called from the erase suspend mode. t he st atus of the program operation can be determined by reading the status register, the same as in the standard program operation. in the event there is a program failure during an erase suspend oper ation, it is necessary to initiate a clear or reset command to return the device to the erase s uspended mode . before trying another program operation on the main memory array, the e rase function will need to be resumed and completed. during erase suspend, valid accesses and commands: ? a ny other non - suspended sector can be r ead . ? a ny other non - suspended sector can be p rogram med. ? status read command ? enter dpb mmo ? dpb set ? dpb clear ? dpb status read ? exit mmo or command set exit ? erase resume command to resume the sector erase operation, an erase resume command must be executed . the device will return back to erasing at which point the status bits will be updated. if another erase resume is attempted it will be ignored. once the device has resumed erase operation a nother erase suspend command can be initiated. while entered in an mmo, erase suspend and r esume is not supported. likewise, entry into a mmo w hile an erase suspend is not supported. 8.10 blank check to confirm if a selected sector is erased a blank check comma nd should be used . reads to the main memory array are not supported during a blank check operation . trying to do so will return unknown data. to execute a blank check operation on a specific sector, write the address (sa)555 and the data 33h after the writ e state controller is in the standby mode. if the device is in a programming or erase mode of operation a blank check command cannot be written.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 35 the status register can confirm if the device is still busy and when it has complete d the blank check operatio n, whether or not the sector is blank . bit 7 , device ready bit of the status register will show if a blank check is being performed by the de vice . bit 5 , erase status bit of the status register will indicate an erased sector when reading a 0 or a non era sed sector when reading a 1 . the device will immediately halt the blank check operation and update the status as soon as any bit in the selected sector is found not to be erased. t he write state controller will return to the standby mode, as soon as the blank check is completed. 8.11 enhanced sector protection methods 8.11.1 enhanced sector protection ( esp ) enhanced sector protection is a method used to enable or disable program and erase operations, in any or all sectors. described in the section are the various methods of protecting data stored in the main memory array. an outline of these methods is shown in the following f igure .
w29gl256s publication release date: jul 0 2 , 201 4 revision c 36 figure 8 - 5 enhanced sector protection ipb program algorithm each sector has a non - volatile individual protection bit ( ipb) and a volatile dynamic protection bit (dpb) associated with it. if in either case the bit is 0, the sector becomes protected from both program and erase operations. program and erase of the ipb bits are protected when the ipb l ock bit is 0. the individual protection mode (default) clears the ipb lock to a 1 during a power up reset or hardware reset . this is done so that the ipb bits are unprotected after device reset. when needed t here is a ipb lock b it command to write the volatile ipb lock bit to a 0 to protect the all the ipb. there is no command in the individual protection mode to clear the ipb lock bit to 1 after it is programmed to 0, except for the power up reset or hardware resets. start individual protection mode (default) set ipb lock bit ipb lock bit locked all ipb not changeable dynamic write protect bit (dpb) sector array individual protect bit (ipb) dpb=0 sector protect dpb=1 sector unprotect ipb lock bit unlocked ipb is changeable dpb 0 dpb 1 dpb 2 dpb + n . . . . sa 0 sa 1 sa 2 sa + n . . . . ipb 0 ipb 1 ipb 2 ipb + n . . . . ipb=0 sector protect ipb=1 sector unprotect ipb=0 ipb=1
w29gl256s publication release date: jul 0 2 , 201 4 revision c 37 the selection of the individual protection mode is set at the factory by programming otp bit in the lock register . when shipped from winbond, all t he sector ipb bits are erased so that all main memory array sectors are unprotected . 8.11.2 ipb lock this one per de vice volatile individual protection bit lock is a bit that will protect all ipb bits. when programmed to 0, it locks all sector ipbs and if the bit is 1, it allows the all sector ipbs to be changed. only after the sector ipbs are configured to the desired state should the ipb lock bit be programmed to 0. n ote the ipb lock command can only program the bit to 0. to erase the ipb lock bit , only a power up reset or a hardware reset will restore the value to 1 to allow sector ipb bits to be changed . there is no software command operation that can clear the ipb lock to a 1. 8.11.3 individual protection bits (ipb) the non - volatile individual protection bits (ipb) is located in a separate non - volatile flash array. there is one ipb bit assigned to each sector. when an ipb is 0 their corresponding sectors is protected from program and erase operations. the ipb can be programmed individually , but are erased as a group. important to note, the write state controller takes care of the p reprogramming and verification prior t o erasure. when p rogramming an ipb bit the typical word programming time is required . to monitor the operation status of an ipb bit programming or erase, dq6 toggle bit i of the data p olling status will toggle until the operation is complete. note ; typical sector erase time is required to e rasing all the ipbs. program or erase command will not execute and will time - out, if the ipb lock is equal 0, without programming or erasing the ipb. the ipb status read command can be used to check t he protection state o f a n ipb for a given sector , but you must first enter the ipb mmo mode . see instruction definition t ables . 8.11.4 dynamic protection bits (dpb) the volatile dynamic protection bits are exclusive for each sector and can be individually changed . only sectors that h ave their ipbs clear to 1 (unprotected) can the dpbs control . by issuing the dpb set or clear command sequences, the dpb are clear to 1 or set to 0, thus placing each sector in the
w29gl256s publication release date: jul 0 2 , 201 4 revision c 38 unprotected or protected state respectively. the dpb can be set to 0 or cle ared to 1 as often as needed. 8.11.5 sector protection bit status summary sector protection status base on ipb, dpb and ipb lock bit weight is as follows: table 8 - 2 sector protection status sector status sector protection bit status ipb lock ipb dpb unprotected: ipb and dpb are changeable 1 1 1 protected : ipb and dpb are changeable 1 1 0 protected: ipb and dpb are changeable 1 0 1 protected: ipb and dpb are changeable 1 0 0 unprotected: dpb is changeable 0 1 1 protected: dpb is changeable 0 1 0 protected: dpb is changeable 0 0 1 protected: dpb is changeable 0 0 0 8.11.6 lock register the lock register is a non - volatile one time programmable ( otp ) register where the bits control protection of the ssr, and the default individual protection mode, programmed at the factory . the security sector region (ssr) protection bits are otp and once programmed (locked) ; there is no command for unlocking the protected portion of the security se ctor region. at this point no program or erase operations are allow in the ssr. the lock register programming time is typically the same as word programming. monitoring data polling status dq6 toggle bit i during a lock register programming internal algori thm will toggle until the operation is finished. another method to monitor the programming status of the lock register can be done reading the status registers bit 4 and 7. see status register o perations for information on these status bits. the reserved bits must be 1 (masked), when programming the lock register bits. table 8 - 3 lock register name bit default value reserved 15 - 9 1 reserved 8 0 reserved 7 x ssr customer lock bit 6 1 reserved 5 1
w29gl256s publication release date: jul 0 2 , 201 4 revision c 39 reserved 4 1 reserved 3 1 reserved 2 1 individual protection mode (factory locked) 1 0 ssr factory lock bit 0 0 8.12 security sector region the security sector region (ssr) mmo provides an extra flash memory area that can be programmed once and permanently protected from further changes. the ssr is 1024 bytes in length. it consists of two 512 bytes regions, factory locked security sector region and 512 bytes for customer locked s ecurity sector region. the secure silicon entry command sequence contains the sector address; this will overlay the security sector region address map on the main memory array selected sector . the overlay starts at location 0 in the selected sector. while the ssr mmo is e ntered the contents of locations exceeding the maximum ssr mmo address of that sector are consider as undefined data. table 8 - 4 security sector re gion word address range content size (sa) + 0000h to 00ffh factory locked security sector region 512 bytes (sa) + 0100h to 01ffh customer locked security sector region 512 bytes (sa) + 0200h to ffffh undefined 127 kbytes
w29gl256s publication release date: jul 0 2 , 201 4 revision c 40 8.13 monitoring device status status register, data polling and the ready/busy# (ry/#by) signal are the three methods for monitoring internal algorithms status . 8.13.1 status register the status register mmo is a 16 - bit register that provides status of program and erase operations. the status register read command is a two cycle command. first cycle overlays the contents of the status register in all locations of the device address space. the second cycle reads the information contents of the s tatus register. the status register mmo is exited automatically after the read access. after the status register read access, #ce or #oe must go high for a period of t ceph or t oeph , respectively to return to the active address space at the time the initial status register read command was executed. some of the status r egister bits are associated to the results indicating succ ess / failure of the most recently completed internal algorithm, while remaining bits are for current status of an internal algorithm that is in progress, suspend ed or has completed. the upper 8 bits dq[15:8] are reserved. they are undefined bits that should be treated as don't care and ignore d . the clear status register command will turn results related bits to 0, bu t will not affect the current state bits. table 8 - 5 status register bit # bit description reset stat us busy stat us read stat us 15:8 reserved x invalid x 7 device ready bit 1 0 1 6 erase suspend status bit 0 invalid erase not suspended =0 erase is suspended =1 5 erase status bit 0 invalid erase successful =0 erase fail =1 4 program status bit 0 invalid program successful =0 program fail =1 3 write buffer abort status bit 0 invalid program not aborted =0 program aborted during write to buffer command =1 2 program suspend status bit 0 invalid no program in suspension =0 program in suspension =1 1 sector lock status bit 0 invalid s ec tor not locked during operation=0 sector locked error =1 0 reserved 0 invalid x notes:
w29gl256s publication release date: jul 0 2 , 201 4 revision c 41 1. dq 7 is 1 when there is no i nternal algorithm in progress in the device. 2. dq[ 6 : 1 ] are valid only if dq 7 is 1 . 3. all bits are put in their reset status by power - up reset or hardware reset. 4. dq[ 5 : 3 , 1 ] is cleared to 0 by the clear status register command or reset command. 5. upon issuing the erase suspend command, the user must continue to read status until dq7= 1. 6. dq6= 0 by the erase resume command. 7. dq5 indicates either a success or failure of the mos t recent erase operation. 8. dq4 indicates a success or failure of the most recent program operation. 9. during erase suspend, programming to the suspended sector, will cause program failure and set the dq4= 1. 10. upon issuing the program suspend command, the user must continue to read status until dq7= 1. 11. dq2= 0 by the program resume command. 12. dq1 indicates the status of the most recent program or erase operation that a program or erase and if the operation failed because the sector was locked. 8.13.2 data polling status during an active internal algorithm the write state controller switches to the data polling mmo to display internal algorithms status to any read access. a single word (2 - bytes) of status information is available in all locations of the devi ce address space. in the status word there are several bits to determine the status of an internal algorithms. these are the dq bits as they appear on the i/o data bus during a read access while an internal alg orithms is in progress. the upper byte (dq[15: 8 ]) , dq4, and dq0 are reserved and are undefined data and should be treat ed as don't care. see data polling status table . 8.13.2.1 d ata# polling (dq7) i / o pin dq7 is the data# polling bit that indicates whether the device has an internal algorithm in progress o r ha s completed. data# polling becomes valid on dq7 on the last rising edge of #we after a program or erase command sequence. during a write buffer programming operation, the final word being programmed in the write buffer - page is the only time data# polling i s valid. polling status is undefined at any other location. the device outputs complement of the data on dq7 d uring an internal program algorithm. the same applies during erase suspend mode while a programming operation is in effect. the device outputs the programmed data bit to dq7 of the last word programmed after the internal program algorithm has complete . note the device allows only reading array data during a program suspend . a program address falling in a protected sector will cause data# polling on dq7 to be active for approximately 20 s, at which time the device returns to reading the main memory array .
w29gl256s publication release date: jul 0 2 , 201 4 revision c 42 during the internal erase o r blank check algorithms, data# polling produces a 0 on dq7. when the algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a 1 on dq7. this is similar to the complement data polling output described for the internal program algorithm . a ddress es must be within the sector selected for erase to read valid status on dq7. if the sector selected for erasing is protected and an era se command sequence is written, dq7, data# polling is active for approx . 100 s, then the device returns to reading the main memory array . when dq7 has changed from the complement to true data, valid data can be read on dq [1 5 :0] on the next read cycles. this is because dq7 may change independently with dq[6: 0 ] while output enable (#oe) is held low . see data# polling (during embedded algorithms) figure or data polling status table these shows the outputs for dq7, d ata# polling . figure for write buffer programming operation with data polling status shows the data# polling. dq7 d ata # p oll ing status may only be read : ? at t he address of the last word loaded into the write buffer for a write buffer programming operation; ? t he location of a single word programming operation. ? a location in a sector being erased or blank checked. figure 8 - 6 data# polling algorithm note: dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 43 8.13.2.2 dq6: toggle bit i data io pin, dq6 ( toggle bit i ) , when monitored can indicate if there is an internal program or erase algorithm in progress or has complete d. it also can indicate whether the device is in a program or era se suspend ed mode. toggle bit i , is valid and can be read at any address after the rising edge of the last #we pulse in a program or erase operation command sequence . successive read cycles to any address d uring an i nternal program or e rase algorithm opera tion will cause dq6 to toggle. dq6 stops toggling when either the program or erase operation has complete. after the execution of an e rase command sequence and that selected sector is protected, dq6 will toggle for about 100s at which time the write state cont roller returns to the standby mode . data io pins dq6 and dq2 together can determine whether a sector is actively erasing or eras e - suspended. when the device has an i nternal e rase algorithm in pro gress , dq6 will toggle . if the device en ters a program suspend o r erase suspend mode, dq6 will stop toggling. to determine which sectors are erasing or erase suspended , dq2 must also be monitored. alternative to this , dq7 can be used ( see dq7: data# polling ). during the erase suspend program mod e dq6 also toggles and once the internal program algorithm has finished, dq6 will stop toggling . refer to the data polling status table, toggle bit program flowchart, dq2: toggle ii section, reading toggle bits dq6/dq2 section and the toggle bit timing dia grams for more information. 8.13.2.3 dq3: sector erase timer to determine whether or not a sector erase has begun after a sector erase command sequence , dq3 may be monitored. refer to sector section for more details. a fter the sector erase command has been entered, it is recommended to read the status of dq7 (data# polling) or dq6 (toggle bit i) to determine that the device has received the command sequence, followed by read ing dq3. if internal erase algorithm has begun , then dq3 should have a value of 1 . refer data polling status table for more information. 8.13.2.4 dq2: toggle bit ii data io pin, dq2 ( toggle bit ii ) when accompanied with dq6 (toggle bit i) , monitors whether the selected sector is actively performing an internal erase algorithm or if the sector is erase - suspended. toggle bit ii status becomes valid after the command sequence and the final rising edge of #we pulse .
w29gl256s publication release date: jul 0 2 , 201 4 revision c 44 dq2 toggles when read at addresses within the selected sector that which the erase algorithm was started. u s e either #oe or #c e to control the read cycles. monitoring just dq2 is not enough to tell whether the sector is currently erasing or is in an erase - suspended state . by comparing dq6 which indicates if the device is currently erasing, or is in an erase suspend state , but is not capable of distinguish ing the selected sector for erase. so, to discern the correct sector and mode of operation, both status bits is required. refer to the data polling status table , toggle bit program flowchart , dq2: toggle ii section, reading toggl e bits dq6/dq2 section an d the toggle bit waveform figure for more information.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 45 8.13.2.5 toggle bits dq6/dq2 in order to discern toggle bit status, dq7 - dq0 must be read at least twice in a row to determine if a toggle bit is actually toggling. if it is determine d that the toggle bit has stopped toggling, this would indicate that the device has either complete d the program or erase operation. this being the case, on the next read cycle array data on dq15 - dq0 can be read. i f it is determines that the toggle bit is still toggling, the n dq5 (exceeded timing limits) should be read to see if the current operation has exceeded its timed limit (dq5=1). if the value of dq5 is 1 then another read of the toggle bit should be done in case dq5 went high at the same time the toggle bit stop toggling . a successful completion of a program or erase operation is indicated by the toggle bit has stopped togg ling . if the toggle bit is toggling, the operation did not complete successfully and the n must issue the reset command to retur n to reading array data. refer to toggle bit program figure .
w29gl256s publication release date: jul 0 2 , 201 4 revision c 46 figure 8 - 7 toggle bit program notes: 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to 1. see text. 8.13.2.6 dq5: exceeded timing limits there is in place a specified internal pulse count for program or erase operations that when exceeded, dq5 value will be equal to 1. this is considered a fail for a program or e rase operation that has not completed successfully. in this situation , a reset command must be executed to return back to a read array mode. it is possible that the device will continue to indicate busy for up to 2 s following the reset command.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 47 8.13.2.7 dq1: writ e - to - buffer abort write - to - buffer operation was aborted if dq1 equals 1 . if this happens , a write - to - buffer - abort - reset command sequence must be executed to bring the wri te state controller to standby and clear the status register failed bits. for more details, s ee write buffer programming section . table 8 - 6 data polling status operation dq7 2 dq6 dq5 1 dq3 dq2 2 dq1 4 ry/#by standard mode internal program algorithm dq7# toggle 0 n/a no toggle 0 0 reading within erasing sector 0 toggle 0 1 toggle n/a 0 reading outside erasing sector 0 toggle 0 1 no toggle n/a 0 program suspend mode 3 reading within program suspended sector invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) 1 reading within non - program suspended sector data data data data data data 1 erase suspend mode reading within erase suspended sector 1 no toggle 0 n/a toggle n/a 1 reading within non - erase suspend sector data data data data data data 1 programming within non - erase suspended sector dq7# toggle 0 n/a n/a n/a 0 write - to - buffer 4 busy state dq7# toggle 0 n/a n/a 0 0 exceeded timing limits dq7# toggle 1 n/a n/a 0 0 abort state dq7# toggle 0 n/a n/a 1 0 notes: 1. dq5 switches to '1' when an internal program or internal erase operation has exceeded the maximum timing limits. see dq5: exceeded timing limits for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. data are invalid for addresses in a program suspended line. 4. dq1 indicates the write - to - buffer abort status during write - buffer - programming operations. 8.14 enhanced variable i/o the data i/o maximum drive and receive voltage s are determined by the e vio supply. this feature allows the device io pins to be compatible with signal buses that have different voltag e levels than the core device voltage. 8.15 ready/#busy the ready/#busy (ry/#by) is a dedicated output pin that indicates whether a hardware reset, a power up reset, or an internal algorithm operation is in progress or has finished . a v alid output from the ry/# by is after the falling edge of #reset, vcc is higher than vcc minimum during power up
w29gl256s publication release date: jul 0 2 , 201 4 revision c 48 reset or after the rising edge of the final #we pulse during a command sequence. the ry/#by pin is an open drain output that should have a pull up resistor tied to e vio . while the ready/#b usy output is high (ready), the device is capable of reading data in the read, erase suspend, or in standby modes. when the device is actively performing an erase, program, or reset operation, the ry/#b y output is low (busy), including i n an erase suspend programming mode. a reset command needs to be executed and status r egister bits 4 and 5 need to be cleared if a program or erase operation fail ed as a result of a timeout or a locked sector leaving the ry/#by in a low state (busy) . refer to the data polling status table for ready/#busy output status. 8.16 hardware data protection option s 8.16.1 write protect (#wp) the lowest or highest sector is protected from program or erase operations while write protect ( #wp ) equals v il , independent of the enhanced sector protection ( esp ) configuration. consequently, if #wp equals v ih , the lowest or highest address sector is not protected by the #wp. the wrote protect pin has an internal pull - up circuit so the default is at v ih . it is important to note the high or low sector protection depends on the device ordering option. 8.16.2 write pulse glitch protection glitch pu lses of less than 5 ns on the #we pin will not initiate a write cycle. 8.16.3 power up write inhibit during power up reset, #reset, #ce, #we, and #oe are ignored . the device is unable to be selected, commands are not accepted on the rising edge of #we, and will not drive outputs during a power up reset . during a power - up reset t he command state machine (c sm) and write state controller are reset to their standby modes, ready for reading array data . before the end of power up re set (t vcs ), #ce or #oe must go to v ih . 8.16.4 logical inhibit write cycles are prevented by holding #oe at v il , or #ce at v ih , or #we at v ih . to start a w rite cycle, #ce and #we must be equal to v il while #oe is equal to v ih .
w29gl256s publication release date: jul 0 2 , 201 4 revision c 49 8.17 inherent data protection 8.17.1 command prot ection internal algorithms are started by writing command sequences into the write state controller command memory. the command memory array is not readable from the bus interface and has no memory map overlay . each bus interface write is a command or a se gment of a command sequence to the device. the write state controller analyses the address and data in each write transfer to decide whether the write is part of a legitimate command sequence. when a correct command sequence is finished the write state controller will start the appropriate internal algorithm . writing an incorrect command sequence, can most likely result in the write state controller returning to its standby mode . however, there is a possibility that an improper command s equence may cause the device to go into an unknown state, in that case a reset command must be executed or possibly a hardware reset, to return the write state controller to its standby mode.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 50 8.18 operating modes and signal states table table 8 - 7 interface conditions mode signal page read random read read without disabled 3 write automatic sleep 1,2 standby hardware reset power up reset vcc vcc min vcc min vcc min vcc min vcc min vcc min vcc min vcc min e vio e vio min vcc e vio min e vio min vcc e vio min vcc e vio min vcc e vio min vcc e vio min vcc e vio min vcc #ce v il v il v il v il v il v ih x x #oe v il v il v ih v ih x x x x #we v ih v ih v ih v il x x x x #reset v ih v ih v ih v ih v ih v ih v il x a[23:0] a[23:4] valid a[3:0] modified valid valid valid valid x x x dq[15:0] valid output valid output hi - z valid input available output hi - z hi - z hi - z this table describes the required condition of each interface signal for each operating mode. legend: x = dont care valid = all bus signals have stable l or h level modified = valid state different from a previous valid state available = read data is internally stored with output driver controlled by #oe notes: 1. #we and #oe cannot be at v il at the same time. 2. read with output disable is a read initiated with #oe high . 3. automatic sleep is a read/write operation where data has been driven on the bus for an extended period, without #ce going high and the device internal logic has gone into standby mode to conserve power.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 51 8.19 instruction definition tables table 8 - 8 read, write, program and erase definitions read, write, program and erase definitions command sequence 1 cycles bus cycles 2 - 5 1 2 3 4 5 6 7 add data add data add data add data add data add dat a add data read 6 1 ra rd reset/mmo exit 7 , 1 4 1 xxx f0 status register read 2 555 70 xxx rd status register clear 1 555 71 word program 4 555 aa 2aa 55 555 a0 pa pd write to buffer 6 555 aa 2aa 55 sa 25 sa wc wbl pd wbl pd program buffer to flash (confirm) 1 sa 29 write - to - buffer - abort reset 11 3 555 aa 2aa 55 555 f0 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspen d/program suspend legacy method 9 1 xxx b0 erase resu me/program resume legacy method 10 1 xxx 30 program suspend enhanced method 1 xxx 51 program resume enhanced method 1 xxx 50 blank check 1 (sa) 555 33
w29gl256s publication release date: jul 0 2 , 201 4 revision c 52 table 8 - 9 cfi - id (autoselect) definitions cfi - id (autoselect) definitions command sequence 1 cycles bus cycles 2 - 5 1 2 3 4 5 6 7 add data add data add data add data add data add data add data id (autoselect) entry 3 555 aa 2aa 55 (sa) 555 90 cfi enter 8 1 (sa) 55 98 cfi - id read 1 xxx rd reset/mmo exit 7 , 1 4 1 xxx f0 table 8 - 10 security sector region command definitions security sector region command definitions command sequence 1 cycles bus cycles 2 - 5 1 2 3 4 5 6 7 add data add data add data add data add data add data add data ssr entry 3 555 aa 2aa 55 (sa) 555 88 read 6 1 ra rd word program 4 555 aa 2aa 55 555 a0 pa pd write to buffer 6 555 aa 2aa 55 sa 25 sa wc wbl pd wbl pd program buffer to flash (confirm) 1 sa 29 write - to - buffer - abort reset 11 3 555 aa 2aa 55 555 f0 ssr exit 11 4 555 aa 2aa 55 555 90 xx 0 reset/mmo exit 7 , 1 4 1 xxx f0
w29gl256s publication release date: jul 0 2 , 201 4 revision c 53 table 8 - 11 lock register command set definitions lock register command set definitions command sequence 1 cycles bus cycles 2 - 5 1 2 3 4 5 6 7 add data add data add data add data add data add data add data lock register entry 3 555 aa 2aa 55 555 40 program 13 2 xxx a0 xxx pd read 13 1 0 rd command set exit 12 , 1 4 2 xxx 90 xxx 0 reset/mmo exit 7 , 1 4 1 xxx f0 table 8 - 12 ipb non - volatile sector protection command set definitions ipb non - volatile sector protection command set definitions command sequence 1 cycles bus cycles 2 - 5 1 2 3 4 5 6 7 add data add data add data add data add data add data add data ipb entry 3 555 aa 2aa 55 555 c0 ipb program 1 5 2 xxx a0 sa 0 all ipb erase 1 5 2 xxx 80 0 30 ipb read 1 5 1 sa rd (0) command set exit 12 , 1 4 2 xxx 90 xxx 0 reset/mmo exit 7 , 1 4 1 xxx f0
w29gl256s publication release date: jul 0 2 , 201 4 revision c 54 table 8 - 13 global non - volatile sector protection freeze command set definitions global non - volatile sector protection freeze command set definitions(ipb lock bit) command sequence 1 cycles bus cycles 2 - 5 1 2 3 4 5 6 7 add data add data add data add data add data add data add data ipb lock entry 3 555 aa 2aa 55 555 50 ipb lock bit cleared 2 xxx a0 xxx 0 ipb lock status read 15 1 xxx rd (0) command set exit 12 , 1 4 2 xxx 90 xxx 0 reset/mmo exit 1 4 1 xxx f0 table 8 - 14 dpb volatile sector protection command set definitions dpb volatile sector protection command set definitions command sequence 1 cycles bus cycles 2 - 5 1 2 3 4 5 6 7 add data add data add data add data add data add data add data dpb mmo entry 3 555 aa 2aa 55 555 e0 dpb erase 1 5 2 xxx a0 sa 1 dpb pgm 1 5 2 xxx a0 sa 0 dpb status read 1 5 1 sa rd (0) command set exit 12 , 1 4 2 xxx 90 xxx 0 reset/mmo exit 1 4 1 xxx f0
w29gl256s publication release date: jul 0 2 , 201 4 revision c 55 legend: x = don't care. ra = address of the memory to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. pd = data to be programmed at location pa. sa = address of the sector selected. address bits a23 - a16 uniquely select any sector. wbl = write buffer location. the address must be within the same line. wc = word count is the number of write buffer locations to load minus 1. notes: 1. see interface condition table for description of bus operations. 2. all values are in hexadecimal. 3. except for the following, all bus cycles are write cycle: read cycle during read, id/cfi read (manufacturing id / device id), indicator bits, security sector region read, ssr lock read, and 2nd cycle of status register read. 4. data bits dq15 - dq8 are don't ca re in command sequences, except for rd, pd, wc and pwd. 5. address bits a23 - a11 is don't care for unlock and command cycles, unless sa or pa required. (a23 is the highest address pin.). 6. no unlock or command cycles required when reading array data. 7. the reset c ommand is required to return to reading array data when device is in the cfi - id ( autoselect ) mode, or if dq5 goes high (while the device is providing status data). 8. command is valid when device is ready to read array data or when device is in cfi - id ( autose lect ) mode. 9. the system can read and program/program suspend in non - erasing sectors, or enter the cfi - id mmo, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 10. the erase resume/program resume command is valid only during the erase suspend/program suspend modes. 11. issue this command sequence to return to read mode after detecting device is in a write - to - buffer - abort state. important: the full command sequence is required if resetting out of abort. 12. the exit command returns the device to reading the array. 13. all lock register bits are one - time programmable. the program state = 0 and the erase state = 1. also, the individual protection mode lock bit cannot be programmed at the same time or the lock register bits program operation aborts and returns the device to read mode. lock register bits that are reserved for future uses are undefined and may be 0s or 1's. 14. if any of the entry commands was issued, an exit command must be issued to reset the device into read mo de.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 56 15. protected state = 00h, unprotected state = 01h. the sector address for dpb set, dpb clear, or ipb program command may be any location within the sector - the lower order bits of the sector address are don't care.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 57 8.20 common flash interface and device id ( cfi - id) the manufacturer id, device id, sector protection status, and basic feature information for the device are available when the device id por tion of the mmo is read, locations 0h to 0fh . the sector protection status can be read by entering the cfi - id command which contains the sector address (sa) and location 02h. if another sector protection status is required, it will be necessary to exit id mmo and re - enter the cdi - id command again with the new sector address. reading location 02h requires an access time of t acc , #ce should go high before the read and to initiate an asynchronous read access #ce should return low again. page mode read is not support for reading between location 02h and th e other id locations . however, page mode read supports read s between id locat ions other than 02h . table 8 - 15 id (autoselect) address map description address data manufacture id (sa) + 0000h 00efh device id (sa) + 0001h 227eh protection verification (sa) + 0002h 0000h/0001h indicator bits dq15 - dq08 = 1 (reserved) dq7: factory locked security sector region 1 = locked, 0 = not locked dq6: customer locked security sector region 1 = locked , 0 = not locked dq5 = 1 (reserved) dq4 - wp# protects 0 = lowest address sector , 1 = highest address sector dq3 - dq0 = 1 (reserved) (sa) + 0003h same as description rfu (sa) + 0004h reserved (sa) + 0005h reserved (sa) + 0006h reserved (sa) + 0007h reserved (sa) + 0008h reserved (sa) + 0009h reserved (sa) + 000ah reserved (sa) + 000bh reserved lower software bits bit 0 : status register support 1 = yes, 0 = no bit 1 :dq p olling support 1 = yes, 0 = no bit 3 - 2 : command set support 11 = reserved 10 = reserved 01 = reduced command set 00 = classic command set bits 4 - 15: reserved = 0 (sa) + 000ch 0003h upper software bits (sa) + 000dh reserved
w29gl256s publication release date: jul 0 2 , 201 4 revision c 58 description address data device id (sa) + 000eh 2222h device id (sa) + 000fh 2201h
w29gl256s publication release date: jul 0 2 , 201 4 revision c 59 table 8 - 16 cfi query identification string description address data query - unique asii string qry (sa) + 10h 0051h (sa) + 11h 0052h (sa) + 12h 0059h primary vendor instruction set and control interface id code (sa) + 13h 0006h (sa) + 14h 0000h address for primary algorithm extended query table (sa) + 15h 0040h (sa) + 16h 0000h alternate vendor instruction set and control interface id code (sa) + 17h 0000h (sa) + 18h 0000h address for alternate algorithm extended query table (sa) + 19h 0000h (sa) + 1ah 0000h table 8 - 17 cfi system interface string description address data vcc supply minimum program/erase voltage (sa) + 1bh 0027h vcc supply maximum program/erase voltage (sa) + 1ch 0036h vpp supply minimum program/erase voltage (sa) + 1dh 0000h vpp supply maximum program/erase voltage (sa) + 1eh 0000h typical timeout per single word/byte write, 2 n s (sa) + 1fh 0008h typical timeout for maximum - size buffer write, 2 n s (00h, not support) (sa) + 20h 0009h typical timeout per individual block erase, 2 n ms (sa) + 21h 0008h typical timeout for full chip erase, 2 n ms (00h, not support) (sa) + 22h 0010h maximum timeout for word/byte write, 2 n times typical (sa) + 23h 0001h maximum timeout for buffer write, 2 n times typical (sa) + 24h 0002h maximum timeout per individual block erase, 2 n times typical (sa) + 25h 0003h maximum timeout for chip erase, 2 n times typical (00h, not support) (sa) + 26h 0003h
w29gl256s publication release date: jul 0 2 , 201 4 revision c 60 table 8 - 18 cfi device geometry definition description address data device size = 2 n in number of bytes (sa) + 27h 0019h flash device interface description (01=asynchronous x16 only) (sa) + 28h 0001h (sa) + 29h 0000h maximum number of bytes in buffer write = 2 n (00h, not support) (sa) + 2ah 0009h (sa) + 2bh 0000h number of erase regions within device (01h:uniform, 02h:boot) (sa) + 2ch 0001h index for erase bank area 1: [2e,2d] = # of same - size sectors in region 1 - 1 [30, 2f] = sector size in multiples of 256k - bytes (sa) + 2dh 00ffh (sa) + 2eh 0000h (sa) + 2fh 0000h (sa) + 30h 0002h index for erase bank area 2 (sa) + 31h 0000h (sa) + 32h 0000h (sa) + 33h 0000h (sa) + 34h 0000h index for erase bank area 3 (sa) + 35h 0000h (sa) + 36h 0000h (sa) + 37h 0000h (sa) + 38h 0000h index for erase bank area 4 (sa) + 39h 0000h (sa) + 3ah 0000h (sa) + 3bh 0000h (sa) + 3ch 0000h
w29gl256s publication release date: jul 0 2 , 201 4 revision c 61 table 8 - 19 cfi primary vendor - specific extended query description address data query - primary extended table, unique ascii string, pri (sa) + 40h 0050h (sa) + 41h 0052h (sa) + 42h 0049h major version number, ascii (sa) + 43h 0031h minor version number, ascii (sa) + 44h 0035h unlock recognizes address (sa) + 45h 001c h erase suspend (2= to both read and program) (sa) + 46h 0002h sector protect (n= # of sectors/group) (sa) + 47h 0001h temporary sector unprotect (1=supported) (sa) + 48h 0000h sector protect/chip unprotect scheme (sa) + 49h 0008h simultaneous r/w operation (0=not supported) (sa) + 4ah 0000h burst mode (0=not supported) (sa) + 4bh 0000h page mode (0=not supported, 01 = 4 word page, 02 = 8 word page) (sa) + 4ch 0003h minimum acc(acceleration) supply (0= not supported), [d7:d4] for volt, [d3:d0] for 100mv (sa) + 4dh 0000h maximum acc(acceleration) supply (0= not supported), [d7:d4] for volt, [d3:d0] for 100mv (sa) + 4eh 0000h wp# protection 04=uniform sectors bottom wp# protect 05=uniform sectors top wp# protect (sa) + 4fh 00xxh program suspend (0=not supported, 1=supported) (sa) + 50h 0001h unlock bypass (0=not supported, 1=supported) (sa) + 51h 0000h secured silicon sector (customer otp area) size 2 n (bytes) (sa) + 52h 0009h software features bit 0: status register polling (1 = supported, 0 = not supported) bit 1: dq polling (1 = supported, 0 = not supported) bit 2: new program suspend/resume commands (1 = supported, 0 = not supported) bit 3: word programming (1 = supported, 0 = not supported) bit 4: bit - field programming (1 = supported, 0 = not supported) bit 5: autodetect programming (1 = supported, 0 = not supported) bit 6: rfu bit 7: multiple writes per line (1 = supported, 0 = not supported) (sa) + 53h 008fh page size = 2 n bytes (sa) + 54h 0005h erase suspend time maximum <2 n (s) (sa) + 55h 0006h program suspend timeout maximum < 2 n (s) (sa) + 56h 0006h embedded hardware reset timeout maximum < 2 n (s) reset with reset pin (sa) + 78h 0006h non - embedded hardware reset timeout maximum < 2 n (s) power on reset (sa) + 79h 0009h
w29gl256s publication release date: jul 0 2 , 201 4 revision c 62 9 electrical specifica tions 9.1 absolute maximum ratings table 9 - 1 absolute maximum ratings parameter values vcc - 0.5v to +4.0v e vio - 0.5v to +4.0v all pins other than #reset 1 - 0.5v to (e vio + 0.5v) #reset 1 - 0.5v to ( vcc + 0.5v) output short circuit current 2 100 ma storage temperature plastic packages - 65c to +150c ambient temperature with power applied - 65c to +125c voltage with respect to ground notes: 1. during signal transitions the i/o or input pins can undershoot vss to a maximum of - 2.0v or overshoot to a maximum of vcc +2.0v for periods of up to 20 ns. see maximum negative overshoot waveform and maximum positive overshoot waveform . minimum dc voltag e on input or i/o pins is - 0.5v and the maximum dc voltage is vcc +0.5v. 2. duration of an output short circuit should not be greater than one second and more than one output may be shorted to ground at a time. 3. permanent damage to the device can be cause by stressing the device above those listed under absolute maximum ratings . device reliability may be affected by operating the device at absolute maximum ratings for a prolonged period of time. 9.1.1 input signal overs hoot figure 9 - 1 max negative overshoot waveform figure 9 - 2 positive overshoot waveform vss vss - 2.0v 20ns 20ns 20ns vcc +2.0v vcc 20ns 20ns 20ns
w29gl256s publication release date: jul 0 2 , 201 4 revision c 63 9.2 operating ranges 9.2.1 temperature ranges industrial (i) ambient temperature (t a ) - 40c to +85c 9.2.2 power supply voltages vcc 2.7v to 3.6v e vio 1.65v to vcc + 200 mv these voltages ranges are guaranteed in which the devices will functionally operation. 9.2.3 power up and power - down vcc must at all times be greater than or equal to e vio . e vio must follow the rise and fall of vcc within 200 mv when e vio is under the e vio minimum. during period of t vcs , which starts the moment that vcc and e vio both raise above the minimum vcc and e vio thresholds and remain s stable, the device will perform power on reset operations and will ignore all inputs until t vcs period has elapsed. table 9 - 2 power up /power - down voltage and timing description parameter min max unit vcc and e vio minimum to first access 1 t vcs 300 s duration of vcc v rst (min) 1 t pd 15 s vcc power supply vcc 2.7 3.6 v notes: 1. not 100% tested.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 64 figure 9 - 3 power - up figure 9 - 4 power - down and voltage drop
w29gl256s publication release date: jul 0 2 , 201 4 revision c 65 9.3 dc characteristics table 9 - 3 dc characteristics description para m test conditions min type 2 max unit input load current i li vin=vss to vcc , vcc = vcc max +0.02 1.0 a output leakage current i lo vout=vss to vcc , vcc = vcc max +0.02 1.0 a vcc active read current i cc1 #ce=v il , #oe=v ih , address switching@ 5 mhz, vcc = vcc max 55 60 ma vcc intra - page read current i cc2 #ce= v il , #oe= v ih , address switching@ 33 mhz, vcc = vcc max 9 25 ma vcc active erase/program current 1 , 2 i cc3 #ce= v il , #oe= v ih , vcc = vcc max 45 100 ma vcc standby current i cc4 #ce, #reset, #oe= v ih , vih= e vio v il =vss, vcc = vcc max 70 100 a vcc reset current 2 , 6 i cc5 #ce= v ih , #reset= v il , vcc = vcc max 7 0 100 u a automatic sleep mode 3 i cc6 v ih = e vio , v il =vss , vcc = vcc max, t acc + 30 ns 3 6 ma vcc current during power up 2 i cc7 #reset= e vio , #ce= e vio , #oe= e vio , vcc = vcc max, 53 80 ma input low voltage 4 v il - 0.5 0.3x e vio v input high voltage 4 v ih 0.7x evio e vio +0.4 v output low voltage 4 , 7 v ol i ol =100a for dq15 - dq0; i ol =2ma for ry/#by 0.15x e vio v output high voltage 4 v oh i oh =100a 0.85x e vio v low vcc power on reset voltage 2 v rst 0.8 v notes: 1. i cc active, if there is an internal algorithm in progress. 2. not 100% tested. 3. when addresses remain stable for the specified period of time, automatic sleep mode will enter the lower power mode. 4. e vio = 1.65v to vcc or 2.7v to vcc . 5. vcc = 3v and e vio = 3v or 1.8v. when e vio is at 1.8v, i/o pins cannot operate at >1.8v. 6. if an internal operation is in progress at the beginning of a reset, the current consumption will remain at the internal operation specification until the internal operation is terminated by the rese t. if no internal operation is in progress when reset has begun or following the termination of an internal operation, i cc7 will draw current during whats left
w29gl256s publication release date: jul 0 2 , 201 4 revision c 66 of the t rph period . at the end of the t rph period, t he device transitions to the standby mode until the next read or write cycle . 7. the ry/#by suggested pull - up resistor for the output is 5k to 10k ohms.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 67 9.4 capacitance characteristics table 9 - 4 connector capacitance for fbga (lfbga64) package description parameter test setup typ max unit input capacitance c in vin = 0 8 9 pf output capacitance c out vout = 0 5 7 pf control pin capacitance c in2 vin = 0 4 8 pf output capacitance ry/#by vout = 0 3 4 pf notes: 1. sampled, not 100% tested. 2. test conditions ta = 25c, f = 1.0 mhz table 9 - 5 connector capacitance for tsop (tsop56) package description parameter test setup typ max unit input capacitance c in vin = 0 7 8 pf output capacitance c out vout = 0 5 6 pf control pin capacitance c in2 vin = 0 3 7 pf output capacitance ry/#by vout = 0 3 4 pf notes: 1. sampled, not 100% tested. 2. test conditions ta = 25c, f = 1.0 mhz table 9 - 6 connector capacitance for tfbga (tfbga56) package description parameter test setup typ max unit input capacitance c in vin = 0 7 8 pf output capacitance c out vout = 0 5 6 pf control pin capacitance c in2 vin = 0 3 7 pf output capacitance ry/#by vout = 0 3 4 pf notes: 1. sampled, not 100% tested. 2. test conditions ta = 25c, f = 1.0 mhz
w29gl256s publication release date: jul 0 2 , 201 4 revision c 68 10 timing specification s 10.1 ac test conditions figure 10 - 1 device under test setup table 10 - 1 test specification parameter description all speeds units output load capacitance, c l 30 pf input rise and fall times 1 1.5 ns input pulse levels 0.0 - e vio v input timing measurement reference levels e vio /2 v output timing measurement reference levels e vio /2 v note: 1. measured between v il max and v ih min. figure 10 - 2 input switching test waveform s
w29gl256s publication release date: jul 0 2 , 201 4 revision c 69 10.2 power up reset and hardware reset decoupling the vcc and e vio power supplies are n ormal precautions that should be taken . generally, a suitable capacitor would be on the order of 0.1 f tied close to the package . table 10 - 2 power on and reset parameters description parameter limit value unit vcc setup time to first access 1 , 2 t vcs min 300 s e vio setup time to first access 1 , 2 t vios min 300 s #reset low to #ce low t rph min 35 s #reset pulse width t rp min 200 ns time between #reset (high) and #ce (low) t rh min 50 ns #ce pulse width high t ceh min 20 ns notes: 1. not 100% tested. 2. ti ming measured from vcc minimum and e vio minimum to v ih on reset and v il on #ce. 3. #reset low is possible during power up reset . if reset is asserted during power up reset , the later period of t rph , t vios , or t vcs will determine when #ce may go low . if #reset stays low after t vios , or t vcs is fulfilled , t rph is measured from the end of t vios , or t vcs . reset is required also to be high t rh before #ce goes low . 4. during power - up, vcc ( e vio - 200 mv ) . 5. the ramp rate for vcc and e vio can be non - linear . 6. t rph must be ? ( t rp + t rh ) . 10.2.1 power up reset the device will draw i cc7 current during power - up reset. as power supplies voltage ramps up, the e vio voltage must remain less than or equal to the vcc voltage. v ih also has to be less than or equal to the e vio voltage . the power - up reset internal algori thm requires a period of t vcs to load all of the write state controller algorithms and default data from non - volatile memory. all control signals incl uding #ce and #reset d uring the power - up reset period are ignored. higher than normal power up reset current during t vcs may occur if #ce is low , but the level of #ce will not influence the power - up reset internal algorithms . for a valid read or write ope ration, #ce or #oe must transition from high to low after the t vcs period . during the period of t vcs, #reset can be high or low . when #reset is low during the period of t vcs , it may stay low at the end of t vcs to keep the device in the hardware reset mode . the device will go to the standby mode if #reset is high at the end of t vcs .
w29gl256s publication release date: jul 0 2 , 201 4 revision c 70 when the power first starts to ramp up and the supply voltage is below v rst , then increases to the operating level minimum, internal device configuration and hardware reset oper ations are initiated. the #ce signal level is ignored for the period of the power up reset operation (t vcs or t vios ). having #reset signal low during this power up reset period is discretionary . however, if #reset is asserted low during power up reset sequence, it must satisfy the hardware reset parameters ; t rp and t rph . in that case , the reset operations will be finished at the later of t vcs , t vios or t rph . figure 10 - 3 power up reset
w29gl256s publication release date: jul 0 2 , 201 4 revision c 71 10.2.2 hardware reset hardware reset is initiated by the #reset signal going to v il . the device will draw i cc7 current during hardware reset (t rph ). the device draws cmos standby current (i cc4 ), if #reset is constantly held at v ss , but if #reset is held at v il and not v s s , the standby current is higher . if #reset is asserted low after t vcs and power - up reset has not completed, in this case the power - up #reset internal algorithms will be performed instead and not hardware #reset, requiring a period of t vcs to complete. aft er the device has completed power up reset and entered the standby mode, a ny transition to the hardware reset mode will initiate the hardware reset internal algorithm. a hardware reset is considerably shorter than a power - up reset ( t rph ) to complete. durin g the hardware reset internal algorithms , any internal algorithm in progress will be terminated and the write state controller is returned to its power up reset mode without reloading write state controller algorithms from non - volatile memory. when the hardware reset internal algorithms finishes , the device will remain in the hardware reset mode, if #reset stays low . if #reset returns high , the device will go in to the standby mode . if #reset is high at the end of the hardware reset internal algorithms , t he device will go in to the standby mode . if the power up reset cycle was not properly finished by the end of t vcs period , a transition to the hardware reset mode will only cause a transition to the power up reset mode and initiate the power - up reset intern al algorithm. this makes sure the device can complete a power - up reset sequence even if some portion of the power up voltage ramp - up causes the power up reset to not initiate or finish properly . during power - up or hardware reset, t he ry/#by pin is low as an indicating the device is busy . figure 10 - 4 hardware reset
w29gl256s publication release date: jul 0 2 , 201 4 revision c 72 10.3 ac characteristics 10.3.1 internal algorithm performance table table 10 - 3 internal algorithm characteristics parameter typ e 2 max 3 unit sector erase time 128 kbyte 5 3 00 20 00 ms single word programming time 1 1 0 2 00 s buffer programming time 2 - byte 1 5 0 20 0 s 32 - byte 1 80 3 50 64 - byte 1 1 10 4 50 128byte 1 1 70 8 50 256byte 1 2 80 140 0 512 - byte 5 0 0 3 00 0 effective write buffer program operation per word 512 - byte 1 s sector programming time 128 kb (full buffer programming) 6 108 192 ms erase suspend/erase resume (t esl ) 40 s program suspend/program resume (t psl ) 40 s erase resume to next erase suspend (t ers ) 7 100 s program resume to next program suspend (t prs ) 7 100 s blank check 6.2 8.5 ms notes: 1. not 100% tested. 2. p rogram and erase typical times presume the following conditions: 25c, 3.0v vcc , a random data pattern and 10,000 cycle s . 3. 90c, vcc = 2.70v, 100,000 cycles, and a random data pattern are considered under worst case conditions . 4. specifications are based upon a 512 - byte write buffer for effective write buffer operations . 5. all words are programmed to 0000h before sector and chip erasure as part of the pre - programming step of the internal erase algorithm . 6. system - level overhead is the time required to execute the bus - cycle sequence for the program command. 7. in order for program or erase operations to progress to comp letion requires the time period to be typical periods. however, a minimum of 60 ns is required between resume and suspend.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 7 3 10.3.2 asynchronous read operations table 10 - 4 read operation e vio = 1.65v to vcc , vcc = 2.7v to 3.6v description symbol vcc =2.7~3.6v alt std min typ max unit valid data output after address e vio = vcc t acc t aa 90 ns e vio =1.65v to vcc 100 ns read period time e vio = vcc t rc 90 ns e vio =1.65v to vcc 100 ns valid data output after #ce low e vio = vcc t ce 90 ns e vio =1.65v to vcc 100 ns page access time e vio = vcc t pacc t pa 15 ns e vio =1.65v to vcc 25 ns valid data output after #ce low e vio = vcc t oe 25 ns e vio =1.65v to vcc 35 ns output hold time from addresses, #ce or #oe, whichever occurs first e vio = vcc t oh 0 ns e vio =1.65v to vcc 0 ns chip enable or output enable to output hiz 1 e vio = vcc t df 15 ns e vio =1.65v to vcc 20 ns output enable hold time 1 read e vio = vcc t oeh 0 ns e vio =1.65v to vcc 10 ns toggle and data# polling e vio = vcc 5 e vio =1.65v to vcc 8 note : 1. not 100% tested. figure 10 - 5 back to back read (tacc) operation
w29gl256s publication release date: jul 0 2 , 201 4 revision c 74 figure 10 - 6 back to back read operation (trc) note: a back to back operation , in which #ce remains low between accesses, requires an address change to initiate the second access. figure 10 - 7 page read note: word configuration: toggle a0, a1, a2, and a3.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 75 10.3.3 asynchronous write operations table 10 - 5 write operations description symbols e vio = vcc =2.7~3.6v alt std min typ max unit write cycle time 1 t wc 60 ns address setup time t as 0 ns address setup time to #oe low during toggle bit polling t aso 15 ns address hold time t ah 45 ns address hold time from #ce or #oe high during toggle bit polling t aht 0 ns data setup time t ds 30 ns data hold time t dh 0 ns output enable high during toggle bit polling or following status register read. t oeph 20 ns read recovery time before write (#oe high to #we low) t ghwl 0 ns #ce setup time t cs 0 ns #ce hold time t ch 0 ns #we pulse width t wp 25 ns #we pulse width high t wph 20 ns note: 1. not 100% tested. figure 10 - 8 back to back write operation
w29gl256s publication release date: jul 0 2 , 201 4 revision c 76 figure 10 - 9 back to back (#ce v il ) write operation figure 10 - 10 write to read (t acc ) operation
w29gl256s publication release date: jul 0 2 , 201 4 revision c 77 figure 10 - 11 write to read (tce) operation figure 10 - 12 read to write (#ce v il ) operation
w29gl256s publication release date: jul 0 2 , 201 4 revision c 78 figure 10 - 13 read to write (#ce toggle) operation table 10 - 6 erase/program operations description symbol e vio = vcc =2.7~3.6v alt std min typ max unit write buffer program operation (512 - byte) t whwh1 5 0.5 3 m s effective write buffer program operation per word 2 , 3 1 s program operation per word 1 0 2 00 s sector erase operation 1 t whwh2 0. 3 2 s erase/program valid to ry/#by delay t busy 80 ns latency between read and write operations 4 t sr_ w 30 ns erase suspend latency t esl 40 s program suspend latency t psl 40 s ry/#by recovery time t rb 0 s notes: 1. not 100% tested. 2. for one 512 bytes programmed. 3. effective write buffer specification is based upon a 256 - word write buffer operation 4. upon the rising edge of #we, must wait t sr_ w before switching to another address. 5. see internal algorithm characteristics table for specific values
w29gl256s publication release date: jul 0 2 , 201 4 revision c 79 figure 10 - 14 program operation note: pa = program address, pd = program data, d out is the true data at the program address. figure 10 - 15 chip/sector erase operation note : sa = sector address (for sector erase), va = valid address for reading status data.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 80 f igure 10 - 16 data# polling (during internal algorithms) note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. figure 10 - 17 toggle bit (during internal algorithms) note: dq6 will toggle at any read address while the device is busy. dq2 will toggle if the address is within the actively erasing s ector.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 81 figure 10 - 18 dq2 vs. dq6 c omparison timing note: the system may use #oe or #ce to toggle dq2 and dq6. dq2 toggles only when read at an address within the erase - suspended sector. 10.3.4 alternate #ce controlled write operations table 10 - 7 alternate #ce controlled write operations description symbol e vio = vcc =2.7~3.6v alt std min typ max unit write cycle time 1 t wc 60 ns address setup time t as 0 ns address setup time to #oe low during toggle bit polling t aso 15 ns address hold time t ah 45 ns address hold time from #ce or #oe high during toggle bit polling t aht 0 ns data setup time t ds 30 ns data hold time t dh 0 ns #ce high during toggle bit polling t ceph 20 ns #oe high during toggle bit polling t o eph 20 ns read recovery time before write (#oe high to #we low) t ghel 0 ns #we setup time t ws 0 ns #we hold time t wh 0 ns #ce pulse width t cp 25 ns #ce pulse width high t cph 20 ns note: 1. not 100% tested.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 82 figure 10 - 19 back to back (#ce) write operation figure 10 - 20 (#ce) write to read operation
w29gl256s publication release date: jul 0 2 , 201 4 revision c 83 11 package dimensions 11.1 tsop 56 - pin 14x20mm symbol dimension in mm dimension inch min nom max min nom max a - - 1.2 - - 0.047 a1 0.05 - 0.15 0.002 - 0.006 a2 0.95 1.00 1.05 0.037 0.039 0.041 b 0.17 0.22 0.27 0.007 0.009 0.011 b1 0.17 0.20 0.23 0.007 0.008 0.009 c 0.10 - 0.21 0.004 - 0.008 c1 0.10 0.13 0.16 0.004 0.005 0.006 d 20.00 bsc 0.787 bsc d1 18.40 bsc 0.724 bsc e 14.00 bsc 0.551 bsc l 0.50 0.60 0.70 0.020 0.024 0.028 l1 0.25 bsc 0.010 bsc e 0.5 bsc 0.020 bsc r 0.08 - 0.35 0.003 - 0.008 0 - 8 0 - 8 figure 11 - 1 tsop 56 - pin 14x20mm package pin 1 identifier a a1 a2 r l1 l 0.80 ref bottom ejector pin cavity # mark 1 28 29 56 d d1 e b 0.10 c with plating c c1 b b1 base metal e
w29gl256s publication release date: jul 0 2 , 201 4 revision c 84 11.2 thin & fine - pitch ball grid array, 56 ball, 7x9mm ( tf bga 56 ) figure 11 - 2 tfbga - 56, 7x9mm package
w29gl256s publication release date: jul 0 2 , 201 4 revision c 85 11.3 l ow - profile fine - pitch ball grid array, 64 - ball 11x13mm (lfba64) symbol dimension (mm) note min nom max a - - 1.40 profile a1 0.40 - ball height a2 0.60 - body thickness d 13.00 bsc body size e 11.00 bsc body size d1 7.00 bsc matrix footprint e1 7.00 bsc matrix footprint n 64 ball count ?b 0.5 0.6 0.7 ball diameter ee 1.00 bsc ball pitch ed 1.00 bsc ball pitch sd/se 0.50 bsc solder ball placement none depopulated solder balls figure 11 - 3 lfbga 64 - ball 11x13mm package d e a b 0.07 (2x) top view pin a1 corner 0.07 c (2x) ee sd pin a1 corner ? b bottom view se e1 ed d1 h g f e d c b a 8 7 6 5 4 3 2 1 0.15 c 0.15 c 0.25 c // a a2 a1 c side view 64x ? b ? 0.20 ? 0.10 m m m m c c b a
w29gl256s publication release date: jul 0 2 , 201 4 revision c 86 w 29gl 256 s h 9 t winbond standard product w: winbond product family 29gl: 3v (vcc=2.7~3.6v) density 256: 256mb product version s: 58nm sector type h: e vio =1.65v to vcc (2.7~3.6v), uniform sector, highest address sector protected l: e vio =1.65v to vcc (2.7~3.6v), uniform sector, lowest address sector protected acc ess time 9: industrial 90ns packages t: tsop - 56, green (rohs compliant) b: lfbga64, green (rohs compliant) c:tfbga56, green (rohs compliant) 12 ordering information 12.1 ordering part number definitions figure 12 - 1 ordering part numbering notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. contact winbond sales for secured sector lock options. 3. for more details on product versions temperature ranges, contact winbond.
w29gl256s publication release date: jul 0 2 , 201 4 revision c 87 12.2 valid part numbers and top side marking the following table provides the valid part numbers for the w29 gl256s parallel flash memory. please contact winbond for specific availability by density and package type. winbond parallel memories use a 12 - digit product number for ordering. table 12 - 1 valid part numbers and markings package type density product number top side marking tsop - 56 256mb w29gl256sh9t w29gl256sh9t tsop - 56 256mb w29gl256sl9t w29gl256sl9t tfbga56 256mb W29GL256SH9C W29GL256SH9C tfbga56 256mb w29gl256sl9c w29gl256sl9c lfbga64 256mb w29gl256sh9b w29gl256sh9b lfbga64 256mb w29gl256sl9b w29gl256sl9b
w29gl256s publication release date: jul 0 2 , 201 4 revision c 88 13 history table 13 - 1 revision history version date page description a 05 - 07 - 201 3 - first release b 0 2 - 2 1 - 201 4 1. remove tassb 2. vrst from 1v to 0.8v 3. remove nop 4. nc pin change name to rfu/dnu 5. write performance modified to meet character data c 0 7 - 0 2 - 2014 m odify some typo trademarks winbond is a trademark of winbond electronics corporation . all other marks are the property of their respective owner. important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or space ship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. furthermore, winbond products are not intended for applications wherein failure of winb ond products could result or lead to a situation where in personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to ful ly indemnify winbond for any damages resulting from such improper use or sales. information in this document is provided solely in connection with winbond products. winbond reserves the right to make changes, corrections, modifications or improvements to t his document and the products and services described herein at any time, without notice.

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